Role of Oxide/Nitride Interface Traps on the Nanocrystal Memory Characteristics

Author(s):  
Alberto Gasperin ◽  
Andrea Cester ◽  
Nicola Wrachien ◽  
Alessandro Paccagnella ◽  
Cosimo Gerardi ◽  
...  
1994 ◽  
Vol 143 (2) ◽  
pp. 333-339 ◽  
Author(s):  
S. Golubović ◽  
G. Ristić ◽  
M. Pejović ◽  
S. Dimitrijev
Keyword(s):  

Author(s):  
Oymatova Dilorom Ruzimurotovna ◽  

The article discusses the peculiarities of memory and its developmental features, the role of memory in human life, the variability of memory in adolescents, ways to strengthen memory, the relationship of thinking and perception with memory, reading and memory development.


2007 ◽  
Vol 90 (13) ◽  
pp. 132102 ◽  
Author(s):  
F. M. Yang ◽  
T. C. Chang ◽  
P. T. Liu ◽  
P. H. Yeh ◽  
Y. C. Yu ◽  
...  

2018 ◽  
Vol 142 ◽  
pp. 8-13 ◽  
Author(s):  
Amit Malik ◽  
Chandan Sharma ◽  
Robert Laishram ◽  
Rajesh Kumar Bag ◽  
Dipendra Singh Rawal ◽  
...  

2016 ◽  
Vol 06 (01) ◽  
pp. 1650001 ◽  
Author(s):  
Chaitali Chakraborty ◽  
Chayanika Bose

The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal–oxide–semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si[Formula: see text]substrate interface than to SiO2/Al–gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance–voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.


Sign in / Sign up

Export Citation Format

Share Document