Failure Analysis of an Anomalous Subthreshold Current in Nano-Scale NAND Flash Memory

2007 ◽  
Author(s):  
Dong-Ho Lee ◽  
Seung-Woo Shin ◽  
Choon-Kun Ryu ◽  
Jae-Hoon Choi ◽  
Chae-Moon Lim ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Subthreshold Current ◽  
Nano Scale

A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory

2008 ◽  
Author(s):  
Hsin-Heng Wang ◽  
Chiu-Tsung Huang ◽  
Shin-Hsien Chen ◽  
Ricky Kuo ◽  
Sophia Liu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Nano Scale

Issues and Challenges of Cleaning for Nano-Scale NAND Flash Memory Manufacturing

2019 ◽  
Vol 11 (2) ◽  
pp. 11-18
Author(s):  
Choon-Kun Ryu ◽  
Young-Tak Song ◽  
Gyu-An Jin ◽  
Sung-Ki Park
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Nano Scale

Investigation of Sidewall Oxidation on WSixGates for Nano-Scale NAND Flash Memory Cells

2008 ◽  
Vol 47 (10) ◽  
pp. 7818-7821
Author(s):  
Ching-Yuan Ho ◽  
Chenhsin Lien ◽  
Po-Jui Chiang ◽  
Kai-Yao Shih
Keyword(s):  
Flash Memory ◽  
Memory Cells ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Nano Scale

Failure Analysis and Reliability Study of NAND Flash-Based Solid State Drives

2016 ◽  
Vol 2 (2) ◽  
pp. 315 ◽  
Author(s):  
R. Sayyad ◽  
Sangram Redkar
Keyword(s):  
Solid State ◽  
Failure Analysis ◽  
Flash Memory ◽  
Fault Tree Analysis ◽  
Physical Nature ◽  
Systematic Evaluation ◽  
Nand Flash ◽  
Solid State Drives ◽  
Nand Flash Memory ◽  
Reliability Study

<p>The research focuses on conducting failure analysis and reliability study to understand and analyze the root cause of Quality, Endurance component Reliability Demonstration Test (RDT) failures and determine SSD performance capability. It addresses essential challenges in developing techniques that utilize solid-state memory technologies (with emphasis on NAND flash memory) from device, circuit, architecture, and system perspectives. These challenges include not only the performance degradation arising from the physical nature of NAND flash memory, e.g., the inability to modify data in-place read/write performance asymmetry, and slow and constrained erase functionality, but also the reliability drawbacks that limits Solid State Drives (SSDs) performance.  In order to understand the nature of failures, a Fault Tree Analysis (FTA) was performed that identified the potential causes of component failures. In the course of this research, significant data gathering and analysis effort was carried out that led to a systematic evaluation of the components under consideration. </p>

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

Sign in / Sign up

Export Citation Format

Share Document