Time-dependent dielectric breakdown in poly-Si CVD HfO/sub 2/ gate stack

Author(s):  
S.J. Lee ◽  
C.H. Lee ◽  
C.H. Choi ◽  
D.L. Kwong
2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.


2021 ◽  
Vol 68 (5) ◽  
pp. 2220-2225
Author(s):  
Stefano Dalcanale ◽  
Michael J. Uren ◽  
Josephine Chang ◽  
Ken Nagamatsu ◽  
Justin A. Parke ◽  
...  

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.


2007 ◽  
Vol 46 (No. 28) ◽  
pp. L691-L692 ◽  
Author(s):  
Takashi Miyakawa ◽  
Tsutomu Ichiki ◽  
Junichi Mitsuhashi ◽  
Kazutoshi Miyamoto ◽  
Tetsuo Tada ◽  
...  

Author(s):  
Federico Giuliano ◽  
Susanna Reggiani ◽  
Elena Gnani ◽  
Antonio Gnudi ◽  
Mattia Rossetti ◽  
...  

2020 ◽  
Vol 41 (10) ◽  
pp. 1460-1463
Author(s):  
Melissa Arabi ◽  
Xavier Garros ◽  
Jacques Cluzel ◽  
Mustapha Rafik ◽  
Xavier Federspiel ◽  
...  

2013 ◽  
Vol 26 (3) ◽  
pp. 281-296
Author(s):  
E. Atanassova ◽  
A. Paskaleva

The effect of both the process-induced defects and the dopant on the time-dependent-dielectric breakdown in Ta2O5 stacks is discussed. The breakdown degradation is analyzed in terms of specific properties of high-k stacks which make their dielectric breakdown mechanism completely different from that of classical SiO2. The relative impact of a number of factors constituting the reliability issues in Ta2O5-based capacitors (trapping in pre-existing traps, stress-induced new traps generation, the presence of interface layer at Si and the role of the dopant) is clarified.


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