Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits

1986 ◽  
Vol 74 (5) ◽  
pp. 669-683 ◽  
Author(s):  
Y. Savaria ◽  
N.C. Rumin ◽  
J.F. Hayes ◽  
V.K. Agarwal
Author(s):  
Aleksandr Zatsarinny ◽  
Yuri Stepchenkov ◽  
Yuri Diachenko ◽  
Yuri Rogdestvenski

The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance


IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 66485-66495 ◽  
Author(s):  
Mohsen Raji ◽  
M. Amin Sabet ◽  
Behnam Ghavami

2015 ◽  
Vol 55 (1) ◽  
pp. 238-250 ◽  
Author(s):  
Ghaith Bany Hamad ◽  
Syed Rafay Hasan ◽  
Otmane Ait Mohamed ◽  
Yvon Savaria

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