A long-term reliability of adhesive flip chip joints using very thin chips

Author(s):  
A. Seppala ◽  
I. Suominen ◽  
E. Ristolainen
Keyword(s):  
2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.


1999 ◽  
Author(s):  
Brian J. Lewis ◽  
Hilary Sasso

Abstract Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process? The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.


2014 ◽  
Vol 2014 (1) ◽  
pp. 000262-000267
Author(s):  
Daniel J. Duffy ◽  
Lin Xin ◽  
Jean Liu ◽  
Bruno Tolla

One step chip attach (OSCA) materials are dispensable polymeric materials for flip chip assembly, which are designed to flux metallic interconnections and subsequently turn into an underfill upon curing. OSCA materials enable a drastic simplification of the assembly process by combining the reflow (fluxing/soldering), defluxing and capillary underfilling steps used in traditional processing into a single step. One key challenge for the design of OSCA materials is timing the cure kinetics with fluxing activity and solder reflow during processing. A second key challenge is to factor a process-friendly rheological design into the formulation. The OSCA material rheology must allow for high filler loading levels, seamless integration with standard dispensing equipment, flow control during and after dispense (avoid keep out zones), flow during die placement (elimination of voids), after placement (fillet formation) and during reflow. The final key requirements for a functional device are defect-free interconnections combined with optimal thermo-mechanical and water resistant properties of the final underfill to guarantee the long-term reliability of the assembly in various environmental conditions. This paper presents the properties of materials designed by Kester for use in mass reflow processing (OSCA-R). The rheological design principles behind a seamless integration into customer-friendly processes will be presented In addition results illustrating the timing of cure kinetics with fluxing and soldering events during processing will be discussed. Preliminary device reliability results will also be presented for several types of test vehicles including; Si-Si and Si-FR4.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.


Author(s):  
Quang Nguyen ◽  
Jordan C. Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall

In this work, an investigation has been performed on hygrothermally induced die stresses in flip chip assemblies caused by moisture absorption by the underfill encapsulant. Silicon test chips were first applied to perform a variety of measurements of moisture and thermally induced die stresses in flip chip on laminate assemblies. The sample die stresses were first measured after underfill encapsulation and cure, and then subsequently after long term storage (10 years) at room temperature and ambient humidity. The assemblies were then exposed to and 85 °C and 85% RH high humidity harsh environment for various durations, and the die stresses were evaluated as a function of the exposure time. Finally, reversibility tests were conducted to see whether the effects of moisture uptake were permanent. After long term storage, the experimental measurements showed that the normal stresses in the flip chip die relaxed significantly, while the shear stresses exhibited only small variations. In addition, the 85/85 hygrothermal exposure had strong effects, generating tensile die normal stress changes of up to 30 MPa in the flip chip assemblies. Thus, the initial compressive die normal stresses due to flip chip assembly were found to relax significantly during the moisture exposure. Upon fully redrying, it was observed that the moisture-induced stress changes were fully recovered. The results of the experimental measurements were subsequently correlated with predictions from finite element numerical simulations. When performing moisture diffusion modeling, the conventional method is to use a thermal analogy based on the similarity of governing equations of heat transfer and moisture diffusion. However, this method has some drawbacks including giving incorrect results when dealing with time- and temperature-dependent problems or discontinuities in the moisture concentrations at material boundaries. In this study, we have used a new feature in ANSYS v14 to perform coupled multi-physics simulations of the moisture diffusion process without the aforementioned limitations. The simulation results were found to show strong correlations with experimental measurements.


2005 ◽  
Vol 127 (4) ◽  
pp. 446-451 ◽  
Author(s):  
Ming-Hwa R. Jen ◽  
Lee-Cheng Liu ◽  
Jenq-Dah Wu

The work is aimed to investigate the mechanical responses of bare dies of the combination of pure tin∕Al–NiV–Cu Under bump metallization (UBM) and packages of pure tin∕Al–NiV–Cu UBM/substrate of standard thickness of aurum. The mechanical properties under multiple reflow and long term high temperature storage test (HTST) tests at different temperatures and the operational life were obtained. A scanning electron microscope was used to observe the growth of IMC and the failure modes in order to realize their reaction and connection. From the empirical results of bare dies, the delamination between IMC and die was observed due to the tests at 260 °C multiple reflow. However, their mechanical properties were not affected. Nevertheless, the bump shear strength of bare dies were decreased by HTST tests. In package, all the results of mechanical properties by multiple reflow test and HTST test were significantly lowered. It was shown that the adhesion between bump and die reduced obviously as tests going on. As for high temperature operational life test in the conditions of 150 °C and 320 mA (5040A∕cm2), the average stable service time of the package was 892 h, and the average ultimate service time of the package was 1053 h.


1990 ◽  
Vol 203 ◽  
Author(s):  
Wei H. Koh ◽  
S. Mayemura ◽  
W. Kuipers

ABSTRACTLong term reliability of flip-chip bump bonding for application in infrared detector interconnection is investigated. The effectiveness of a thin film nickel as diffusion barrier for reducing indium-gold intermetallic formation is studied by accelerated life test and destructive physical analysis. A new interconnect structure replacing the conventional bump-to-bump configuration is described.


2010 ◽  
Vol 132 (3) ◽  
Author(s):  
D. Blass ◽  
P. Borgesen

The effects of underfill selection on flip chip reliability were always a complex issue. Mechanical optimization of the underfill performance, achieved by the addition of appropriate fillers, is invariably a tradeoff between the adhesion and the coefficient of thermal expansion (CTE) and, thus, also between in-plane and out-of-plane stresses. Another critical concern is the degradation of the underfill in processing and/or long term exposure to operating temperatures and ambient humidity. This is strongly affected by the chemical compatibility with combinations of solder mask, chip passivation, and flux residues. The latter is believed to be responsible for our observation of interactions with the solder alloy, too. As for the effects of glass transition temperatures and CTE, we find materials that were close to optimum for eutectic SnPb to be very far from the best options for lead free joints. We report on two sets of systematic experiments. The first addressed the performance of combinations of underfills, no-clean fluxes, and solder alloys in a JEDEC level 3 moisture sensitivity test. The second one involved thermal shock testing of flip chip assemblies underfilled with one of five different materials after soldering with SnCu, SAC305, and SnPb.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001870-001894
Author(s):  
Terence Q. Collier

When thick gold and tin come into contact the intermetallic formed is not one for long term reliability. AuSn intermetallics can lead to void formation, increased resistance and a very brittle joint that will fail in time. Such intermetallic formations occur when gold stud bumps are brought into contact with Sn based allows. Fine pitched devices, such as optical, typically use gold studs due to the tight pitch and small pad sizes. By transforming the gold to a less benign state the gold stud bumps allow assembly using standard Sn based solders. Such a process is beneficial when cheapers solders can be used as well as standard flip chip assembly equipment. This paper will provide cross sections of gold stud bumps with SAC305 solder after 3X reflow. The 3X reflow is required to demonstrate the capability and reliability of the modified solder joint. Rozalia/Ron ok move from 2.5/3D to FC/WLP 12-21-11.


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