A Reliability-Aware Multi-application Mapping Technique in Networks-on-Chip

2013 ◽  
Author(s):  
F. Khalili ◽  
H. R. Zarandi
Keyword(s):  
Mapping Technique ◽  
Networks On Chip ◽  
Application Mapping ◽  
On Chip

scholarly journals Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Yin Zhen Tei ◽  
Yuan Wen Hau ◽  
N. Shaikh-Husin ◽  
M. N. Marsono
Keyword(s):  
Domain Knowledge ◽  
Large Scale ◽  
Pareto Front ◽  
Mapping Technique ◽  
Network Partitioning ◽  
Application Mapping ◽  
Knowledge Based ◽  
Large Scale Network ◽  
Scale Network ◽  
On Chip

This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC). As the number of intellectual property (IP) cores in multiprocessor system-on-chip (MPSoC) increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA). The initial population of GA is initialized with network partitioning (NP) while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with state-of-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover.

scholarly journals Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

2018 ◽  
Vol 89 ◽  
pp. 103-117 ◽  
Author(s):  
Michael Opoku Agyeman ◽  
Ali Ahmadinia ◽  
Nader Bagherzadeh
Keyword(s):  
Networks On Chip ◽  
Application Mapping ◽  
And Performance ◽  
On Chip ◽  
3D Networks

Application mapping in hybrid photonic networks-on-chip for reducing insertion loss

2018 ◽  
Vol 74 (9) ◽  
pp. 4647-4671 ◽  
Author(s):  
Somayeh Khoroush ◽  
Midia Reshadi ◽  
Ahmad Khademzadeh
Keyword(s):  
Insertion Loss ◽  
Photonic Networks ◽  
Networks On Chip ◽  
Application Mapping ◽  
On Chip

Evaluation of energy and buffer aware application mapping for networks-on-chip

2014 ◽  
Vol 38 (4) ◽  
pp. 325-336 ◽  
Author(s):  
Coşkun Çelik ◽  
Cüneyt F. Bazlamaçcı
Keyword(s):  
Networks On Chip ◽  
Application Mapping ◽  
On Chip

scholarly journals A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 613
Author(s):  
Fen Ge ◽  
Chenchen Cui ◽  
Fang Zhou ◽  
Ning Wu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Optimal Placement ◽  
Networks On Chip ◽  
Core Networks ◽  
Application Mapping ◽  
Mapping Approach ◽  
On Chip ◽  
The One ◽  
Multi Phase ◽  
Many Core

More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications.

scholarly journals An Optimized Nature-Inspired Metaheuristic Algorithm for Application Mapping in 2D-NoC

Sensors ◽  
2021 ◽  
Vol 21 (15) ◽  
pp. 5102
Author(s):  
Saleha Sikandar ◽  
Naveed Khan Baloch ◽  
Fawad Hussain ◽  
Waqar Amin ◽  
Yousaf Bin Zikria ◽  
...  
Keyword(s):  
Network Performance ◽  
Nearest Neighbor ◽  
Mapping Technique ◽  
K Nearest Neighbor ◽  
Application Mapping ◽  
Task Graphs ◽  
Large Application ◽  
Ip Cores ◽  
Cost Metrics ◽  
On Chip

Mapping application task graphs on intellectual property (IP) cores into network-on-chip (NoC) is a non-deterministic polynomial-time hard problem. The evolution of network performance mainly depends on an effective and efficient mapping technique and the optimization of performance and cost metrics. These metrics mainly include power, reliability, area, thermal distribution and delay. A state-of-the-art mapping technique for NoC is introduced with the name of sailfish optimization algorithm (SFOA). The proposed algorithm minimizes the power dissipation of NoC via an empirical base applying a shared k-nearest neighbor clustering approach, and it gives quicker mapping over six considered standard benchmarks. The experimental results indicate that the proposed techniques outperform other existing nature-inspired metaheuristic approaches, especially in large application task graphs.

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