Energy and buffer aware application mapping for networks-on-chip with self similar traffic

2013 ◽  
Vol 59 (10) ◽  
pp. 1364-1374 ◽  
Author(s):  
Coşkun Çelik ◽  
Cüneyt F. Bazlamaçcı
Keyword(s):  
Networks On Chip ◽  
Application Mapping ◽  
Self Similar ◽  
On Chip

scholarly journals Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

2018 ◽  
Vol 89 ◽  
pp. 103-117 ◽  
Author(s):  
Michael Opoku Agyeman ◽  
Ali Ahmadinia ◽  
Nader Bagherzadeh
Keyword(s):  
Networks On Chip ◽  
Application Mapping ◽  
And Performance ◽  
On Chip ◽  
3D Networks

Application mapping in hybrid photonic networks-on-chip for reducing insertion loss

2018 ◽  
Vol 74 (9) ◽  
pp. 4647-4671 ◽  
Author(s):  
Somayeh Khoroush ◽  
Midia Reshadi ◽  
Ahmad Khademzadeh
Keyword(s):  
Insertion Loss ◽  
Photonic Networks ◽  
Networks On Chip ◽  
Application Mapping ◽  
On Chip

Evaluation of energy and buffer aware application mapping for networks-on-chip

2014 ◽  
Vol 38 (4) ◽  
pp. 325-336 ◽  
Author(s):  
Coşkun Çelik ◽  
Cüneyt F. Bazlamaçcı
Keyword(s):  
Networks On Chip ◽  
Application Mapping ◽  
On Chip

scholarly journals A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 613
Author(s):  
Fen Ge ◽  
Chenchen Cui ◽  
Fang Zhou ◽  
Ning Wu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Optimal Placement ◽  
Networks On Chip ◽  
Core Networks ◽  
Application Mapping ◽  
Mapping Approach ◽  
On Chip ◽  
The One ◽  
Multi Phase ◽  
Many Core

More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications.

A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip

2015 ◽  
Vol 24 (08) ◽  
pp. 1550126 ◽  
Author(s):  
Pradip Kumar Sahu ◽  
Kanchan Manna ◽  
Tapan Shah ◽  
Santanu Chattopadhyay
Keyword(s):  
Complexity Analysis ◽  
Network On Chip ◽  
Application Mapping ◽  
Design Time ◽  
Constructive Heuristic ◽  
Underlying Network ◽  
Dynamic Performances ◽  
Self Similar ◽  
On Chip ◽  
Better Than

Mapping constitutes a very important step in network-on-chip (NoC)-based implementation of an application. An application is often represented in the form of an application core graph. The cores of the core graph communicate between themselves using the underlying network. This paper presents a constructive heuristic to statically map applications on two-dimensional mesh-connected NoC. The approach corresponds to a design time decision of attachment of cores to the routers. The mapping results, in terms of overall communication cost metric, have been compared with many well-known techniques reported in the literature and also with an exact method built around integer linear programming (ILP). A thorough complexity analysis of the algorithm has been performed. For smaller benchmarks, the results obtained are same as those for the ILP generated solutions. For benchmarks containing 64 and higher number of cores, the mapping solutions are better than the existing ones. Dynamic performances of the mapped solutions have been compared with respect to synthetically generated self-similar traffic. In many cases, our approach requires less latency and energy per packet than the existing methods while providing higher throughput.

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