An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition

2017 ◽  
Author(s):  
Hamid Tabani ◽  
Jose-Maria Arnau ◽  
Jordi Tubella ◽  
Antonio Gonzalez
Keyword(s):  
Speech Recognition ◽  
Low Power ◽  
Hardware Accelerator ◽  
Ultra Low Power

scholarly journals Time-Encoding-Based Ultra-Low Power Features Extraction Circuit for Speech Recognition Tasks

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 418
Author(s):  
Eric Gutierrez ◽  
Carlos Perez ◽  
Fernando Hernandez ◽  
Luis Hernandez
Keyword(s):  
Feature Extraction ◽  
Speech Recognition ◽  
Power Consumption ◽  
Low Power ◽  
System Level ◽  
Portable Devices ◽  
Cmos Process ◽  
Ring Oscillators ◽  
Ultra Low Power ◽  
Band Pass

Current trends towards on-edge computing on smart portable devices requires ultra-low power circuits to be able to make feature extraction and classification tasks of patterns. This manuscript proposes a novel approach for feature extraction operations in speech recognition/voice activity detection tasks suitable for portable devices. Whereas conventional approaches are based on either completely analog or digital structures, we propose a “hybrid” approach by means of voltage-controlled-oscillators. Our proposal makes use of a bank a band-pass filters implemented with ring-oscillators to extract the features (energy within different frequency bands) of input audio signals and digitize them. Afterwards, these data will input a digital classification stage such as a neural network. Ring-oscillators are structures with a digital nature, which makes them highly scalable with the possibility of designing them with minimum length devices. Additionally, due to their inherent phase integration, low-frequency band-pass filters can be implemented without large capacitors. Consequently, we strongly benefit from power consumption and area savings. Finally, our proposal may incorporate the analog-to-digital converter into the structure of the own features extractor circuit to make the full conversion of the raw data when triggered. This supposes a unique advantage with respect to other approaches. The architecture is described and proposed at system-level, along with behavioral simulations made to check whether the performance is the expected one or not. Then the structure is designed with a 65-nm CMOS process to estimate the power consumption and area on a silicon implementation. The results show that our solution is very promising in terms of occupied area with a competitive power consumption in comparison to other state-of-the-art solutions.

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