Microarchitecture and Design Challenges for Gigascale Integration

2004 ◽  
Author(s):  
S. Borkar
Keyword(s):  
Gigascale Integration ◽  
Design Challenges

Interconnect Limits on Gigascale Integration (GSI)

1997 ◽  
Vol 473 ◽  
Author(s):  
J. A. Davis ◽  
J. D. Meindl
Keyword(s):  
Response Time ◽  
Length Distribution ◽  
Path Model ◽  
System Level ◽  
Wire Length ◽  
Clock Frequency ◽  
Gigascale Integration ◽  
Logic Network ◽  
Binary Switching ◽  
Quantitative Definition

ABSTRACTOpportunities for Gigascale Integration (GSI) are governed by a hierarchy of physical limits. The levels of this hierarchy have been codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Many key limits at all levels of the hierarchy can be displayed in the power, P, versus delay, td, plane and the reciprocal length squared, L-2, versus response time, τ, plane. Power, P, is the average power transfer during a binary switching transition and delay, td, is the time required for the transition. Length, L, is the distance traversed by an interconnect that joins two nodes on a chip and response time, τ, characterizes the corresponding interconnect circuit. At the system level of the hierarchy, quantitative definition of both the P versus td and the L-2 versus τ displays requires an estimate of the complete stochastic wiring distribution of a chip.Based on Rent's Rule, a well known empirical relationship between the number of signal input/output terminals on a block of logic and the number of gate circuits with the block, a rigorous derivation of a new complete stochastic wire length distribution for an on-chip random logic network is described. This distribution is compared to actual data for modern microprocessors and to previously described distributions. A methodology for estimating the complete wire length distribution for future GSI products is proposed. The new distribution is then used to enhance the critical path model that determines the maximum clock frequency of a chip; to derive a preliminary power dissipation model for a random logic network; and, to define an optimal architecture of a multilevel interconnect network that minimizes overall chip size. In essence, a new complete stochastic wiring distribution provides a generic basis for maximizing the value obtained from a multilevel interconnect technology.

Recent developments in vertical cooling crystalliser design

2011 ◽  
pp. 726-733
Author(s):  
Michael Getaz ◽  
Rob Sanders
Keyword(s):  
Motor Drive ◽  
Steady Increase ◽  
Unit Size ◽  
Heat Transfer Characteristics ◽  
Heat Exchange Surface ◽  
Recent Developments ◽  
Cooling Tube ◽  
Good Heat ◽  
Exchange Surface ◽  
Design Challenges

In modern installations vertical cooling crystallisers are now preferred over traditional horizontal units because of the significant benefits they offer, which include larger volumes and smaller floor space, suitability for outdoor installation, higher cooling surface to volume ratios and a better ability to handle highly viscous massecuite, amongst others. Since the first vertical cooling crystallisers were introduced, nearly 40 years ago, there has been a steady increase in their unit size from initial volumes in the 50–200 m3 range up to the present day where the most general unit size is now in the 300–400 m3 range, with even larger units becoming increasingly common. Large crystallisers present some significant design challenges and a good modern vertical cooling crystalliser design requires a robust construction of heat exchange surface, stirrer and drive units coupled with features that promote good heat transfer characteristics and uniform massecuite flow patterns. Careful attention to cooling tube and stirrer arm design and configuration are needed to achieve this, whilst the use of modern planetary gearboxes and variable frequency controlled motor drive units can provide added benefits to boost both performance and reliability. How these design features are incorporated in a modern unit is explained, focusing on cane C massecuite duty and using the Fives Cail and Fives Fletcher units as an example.

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