Compiling for instruction cache performance on a multithreaded architecture

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings. ◽

10.1109/micro.2002.1176269 ◽

2005 ◽

Cited By ~ 6

Author(s):

R. Kumar ◽

D.M. Tullsen

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

Multithreaded Architecture

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Achieving High Instruction Cache Performance With An Optimizing Compiler

The 16th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1989.714559 ◽

2005 ◽

Author(s):

W.W. Hisu ◽

Pohua P. Chang

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

Optimizing Compiler

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Improving Instruction Cache Performance by Dynamic Management of Cache-Image

KIISE Transactions on Computing Practices ◽

10.5626/ktcp.2017.23.9.564 ◽

2017 ◽

Vol 23 (9) ◽

pp. 564-571

Author(s):

Hyo-Joong Suh

Keyword(s):

Cache Performance ◽

Dynamic Management ◽

Instruction Cache ◽

Improving Instruction

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Achieving high instruction cache performance with an optimizing compiler

ACM SIGARCH Computer Architecture News ◽

10.1145/74926.74953 ◽

1989 ◽

Vol 17 (3) ◽

pp. 242-251 ◽

Cited By ~ 22

Author(s):

W. W. Hwu ◽

P. P. Chang

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

Optimizing Compiler

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The impact of code density on instruction cache performance

Proceedings of the 16th annual international symposium on Computer architecture - ISCA '89 ◽

10.1145/74925.74954 ◽

1989 ◽

Cited By ~ 3

Author(s):

P. Steenkiste

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

The Impact ◽

Code Density

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Data Layout for Cache Performance on a Multithreaded Architecture

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_3 ◽

2011 ◽

pp. 43-68 ◽

Cited By ~ 1

Author(s):

Subhradyuti Sarkar ◽

Dean M. Tullsen

Keyword(s):

Data Layout ◽

Cache Performance ◽

Multithreaded Architecture

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Bounding pipeline and instruction cache performance

IEEE Transactions on Computers ◽

10.1109/12.743411 ◽

1999 ◽

Vol 48 (1) ◽

pp. 53-70 ◽

Cited By ~ 103

Author(s):

C.A. Healy ◽

R.D. Arnold ◽

F. Mueller ◽

D.B. Whalley ◽

M.G. Harmon

Keyword(s):

Cache Performance ◽

Instruction Cache

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Optimizing the instruction cache performance of the operating system

IEEE Transactions on Computers ◽

10.1109/12.737683 ◽

1998 ◽

Vol 47 (12) ◽

pp. 1363-1381 ◽

Cited By ~ 9

Author(s):

J. Torrellas ◽

Chun Xia ◽

R.L. Daigle

Keyword(s):

Operating System ◽

Cache Performance ◽

Instruction Cache

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Optimizing instruction cache performance of embedded systems

ACM Transactions on Embedded Computing Systems ◽

10.1145/1113830.1113839 ◽

2005 ◽

Vol 4 (4) ◽

pp. 934-965 ◽

Cited By ~ 5

Author(s):

S. Bartolini ◽

C. A. Prete

Keyword(s):

Embedded Systems ◽

Cache Performance ◽

Instruction Cache

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Bounding worst-case instruction cache performance

Proceedings Real-Time Systems Symposium REAL-94 ◽

10.1109/real.1994.342718 ◽

1994 ◽

Cited By ~ 107

Author(s):

Arnold ◽

Mueller ◽

Whalley ◽

Harmon

Keyword(s):

Cache Performance ◽

Worst Case ◽

Instruction Cache

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The Impact Of Code Density On Instruction Cache Performance

The 16th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1989.714560 ◽

2005 ◽

Cited By ~ 7

Author(s):

P. Steenkiste

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

The Impact ◽

Code Density

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