High Phosphorus Dopant Activation in Germanium Using Laser Spike Annealing

2016 ◽  
Vol 37 (9) ◽  
pp. 1088-1091 ◽  
Author(s):  
William Hsu ◽  
Xiaoru Wang ◽  
Feng Wen ◽  
Yun Wang ◽  
Andrei Dolocan ◽  
...  
Keyword(s):  
Dopant Activation ◽  
High Phosphorus ◽  
Spike Annealing

Issues and Optimization of Millisecond Anneal Process for 45 nm node and beyond

2006 ◽  
Vol 912 ◽  
Author(s):  
Kanna Adachi ◽  
Kazuya Ohuchi ◽  
Nobutoshi Aoki ◽  
Hideji Tsujii ◽  
Takayuki Ito ◽  
...  
Keyword(s):  
Sheet Resistance ◽  
Leakage Current ◽  
Flash Lamp ◽  
Gate Leakage Current ◽  
Junction Depth ◽  
Gate Leakage ◽  
Dopant Activation ◽  
Similar Relation ◽  
Device Integration ◽  
Spike Annealing

AbstractWe have investigated MSA, namely, Laser Spike Annealing (LSA) and Flash Lamp Annealing (FLA), dopant activation technology of source/drain extension for 45 nm node, which can be substituted for spike RTA. Since it is possible to achieve a similar relation between a sheet resistance and a junction depth by using either FLA or LSA, both annealing methods are capable of providing the junction characteristics required by the ITRS target. However, we have noticed that there are three crucial issues from the viewpoints of device integration and CMOSFET performance: junction leakage current, gate leakage current and pattern dependence. In this report, we discuss these issues and indicate how to cope with them.

Shallow Boron Implant Activation

1999 ◽  
Vol 568 ◽  
Author(s):  
A. T. Fiory ◽  
K. K. Bourdelle ◽  
A. Agarwal ◽  
H.-J. Gossmann ◽  
C. S. Rafferty
Keyword(s):  
Sheet Resistance ◽  
Electrical Transport ◽  
Annealing Temperature ◽  
Surface Oxidation ◽  
Heating Rates ◽  
Dopant Activation ◽  
Practical Temperature ◽  
Spike Annealing ◽  
And Diffusion ◽  
Secondary Ion

ABSTRACTBoron was implanted into n-type Si at energies from 500 eV to 1 keV and doses near 1 E14 cm-2and 1E51 cm−2. Electrical activation was achieved by rapid thermal annealing (RTA) in nominally pure N−2and 0.1% 02 with the fastest available heating rates of up to 150 °C/s, cooling rates up to 80 °C/s, and included “spike” anneals with minimum dwell time at peak temperature. Measurements of sheet resistance, Hall coefficient, and secondary ion mass spectroscopy profiling were used to determine dopant activation and diffusion. Surface oxidation was studied by film thickness ellipsometry. Analyses of electrical transport measurements are used to relate junction depths to sheet resistance and their dependence on annealing temperature and time. For spike annealing, junction leakage and adequate activation limits the minimum practical temperature while diffusion limits the maximum practical temperature for formation of shallow junctions.

Ultra-Shallow Junction Formation Technology from the 130 to the 45 nm node

2004 ◽  
Vol 810 ◽  
Author(s):  
Amitabh Jain
Keyword(s):  
High Performance ◽  
Junction Depth ◽  
Implantation Energy ◽  
Dopant Activation ◽  
Complex Interactions ◽  
Materials Research ◽  
Depth Increase ◽  
Motivating Factor ◽  
Spike Annealing ◽  
Ion Implanted

ABSTRACTOne of the main materials challenges of the 130 nm silicon technology node was the need to find a processing solution to the anomalous diffusion behavior of ion-implanted dopants known from three decades of research. Reduction of implantation energy no longer proved sufficient when trying to reduce source/drain extension junction depth, increase abruptness, and limit sheet resistance. Spike-annealing, a new process in which ion implanted silicon could be heated rapidly to temperatures required for dopant activation and then cooled down without dwelling at temperature, adequately addressed the scaling requirements of this node. The resulting junctions achieved high dopant concentration values very close to the surface while limiting junction depth. However, this increased the propensity for dopant migration to overlying layers associated with the source/drain spacer. Loss of device performance due to this and other phenomena became a strong motivating factor for further materials research in order to sustain progress through the 130 nm and 90 nm nodes. Complex interactions between various layers have been understood and the resulting developments in spacer materials have enabled high performance devices. The requirements of the 65 and 45 nm nodes stretch spike-annealing to its limit and newer Ultra-High Temperature anneals must be considered.

Ultra-Shallow Junction Formation Using Rapid Thermal Processing

2008 ◽  
Vol 573-574 ◽  
pp. 305-318 ◽  
Author(s):  
Amitabh Jain
Keyword(s):  
High Performance ◽  
Junction Depth ◽  
Implantation Energy ◽  
Dopant Activation ◽  
Complex Interactions ◽  
Materials Research ◽  
Depth Increase ◽  
Motivating Factor ◽  
Spike Annealing ◽  
Ion Implanted

One of the main materials challenges of the 130 nm silicon technology node was the need to find a processing solution to the anomalous diffusion behavior of ion-implanted dopants known from three decades of research. Reduction of implantation energy no longer proved sufficient when trying to reduce source/drain extension junction depth, increase abruptness, and limit sheet resistance. Spike-annealing, a new process in which ion implanted silicon could be heated rapidly to temperatures required for dopant activation and then cooled down without dwelling at temperature, adequately addressed the scaling requirements of this node. The resulting junctions achieved high dopant concentration values very close to the surface while limiting junction depth. However, this increased the propensity for dopant migration to overlying layers associated with the source/drain spacer. Loss of device performance due to this and other phenomena became a strong motivating factor for further materials research in order to sustain progress through the 130 nm and 90 nm nodes. Complex interactions between various layers have been understood and the resulting developments in spacer materials have enabled high performance devices. The requirements of the 65 and 45 nm nodes stretch spike-annealing to its limit and newer ultra-high temperature anneals must be considered.

Ultrashallow Junction Formation and Gate Activation in Deep-Submicron CMOS

2000 ◽  
Vol 610 ◽  
Author(s):  
P. A. Stolk ◽  
F. N. Cubaynes ◽  
V. M. H. Meyssen ◽  
G. Mannino ◽  
N. E. B. Cowern ◽  
...  
Keyword(s):  
Deep Submicron ◽  
Mos Capacitors ◽  
Dopant Activation ◽  
Fine Grained ◽  
Annealing Conditions ◽  
Activation Level ◽  
Ultrashallow Junction ◽  
B Doping ◽  
Dopant Loss ◽  
Spike Annealing

AbstractThis paper addresses the optimization of ion implantation and rapid thermal annealing for the fabrication of shallow junctions and the activation of polycrystalline silicon gates in deepsubmicron CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by combining low-energy B and As implantation with spike annealing. In addition, experiments using B doping marker superlattices were performed to identify the critical physical effects underlying dopant activation and diffusion. The combination of high ramp rates (∼100 °C/s) and ∼1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without inducing significant thermal diffusion after TED has completed. MOS capacitors were used to identify the implantation and annealing conditions needed for adequate activation of the gate electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing times while improving the gate activation level. The fine-grained crystal structure enhances the de-activation of B dopants in PMOS gates during the thermal treatments following gate activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent 0.18 μm device performance. The feasibility of spike annealing and poly-Si gate materials for 100-nm technology was proven by full integration using gate lengths down to 80 nm.

Laser Crystallization and Dopant Activation of a-Si:H Carrier-Selective Layer in TOPCon Si Solar Cells

2020 ◽  
Vol 10 (5) ◽  
pp. 1283-1289
Author(s):  
George C. Wilkes ◽  
Ajay D. Upadhyaya ◽  
Ajeet Rohatgi ◽  
Mool C. Gupta
Keyword(s):  
Solar Cells ◽  
Laser Crystallization ◽  
Selective Layer ◽  
Dopant Activation ◽  
Si Solar Cells

Annealed high-phosphorus electroless Ni–P coatings for producing molds for precision glass molding

2021 ◽  
Vol 262 ◽  
pp. 124297
Author(s):  
Qian Yu ◽  
Tianfeng Zhou ◽  
Yupeng He ◽  
Peng Liu ◽  
Xibin Wang ◽  
...  
Keyword(s):  
Glass Molding ◽  
Precision Glass Molding ◽  
High Phosphorus ◽  
Electroless Ni
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