Enhanced Operation Characteristics in Poly-Si Nanowire Charge-Trapping Flash Memory Device With SiGe Buried Channel

2014 ◽  
Vol 35 (10) ◽  
pp. 1025-1027 ◽  
Author(s):  
Chun-Yuan Chen ◽  
Kuei-Shu Chang-Liao ◽  
Li-Jung Liu ◽  
Wei-Chieh Chen ◽  
Tien-Ko Wang
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Si Nanowire ◽  
Buried Channel ◽  
Operation Characteristics

Enhanced Programming and Erasing Speeds in P-Channel Charge-Trapping Flash Memory Device With SiGe Buried Channel

2012 ◽  
Vol 33 (9) ◽  
pp. 1264-1266 ◽  
Author(s):  
Li-Jung Liu ◽  
Kuei-Shu Chang-Liao ◽  
Yi-Chuen Jian ◽  
Jen-Wei Cheng ◽  
Tien-Ko Wang ◽  
...  
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Buried Channel

Impacts of Electrical Field in Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Device

2020 ◽  
Vol 41 (12) ◽  
pp. 1766-1769
Author(s):  
Hsin-Kai Fang ◽  
Kuei-Shu Chang-Liao ◽  
Kuan-Chi Chou ◽  
Tzu-Cheng Chao ◽  
Jung-En Tsai ◽  
...  
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Electrical Field ◽  
Operation Characteristics

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

2018 ◽  
Vol 35 (5) ◽  
pp. 057302
Author(s):  
Zhao-Zhao Hou ◽  
Gui-Lei Wang ◽  
Jia-Xin Yao ◽  
Qing-Zhu Zhang ◽  
Hua-Xiang Yin
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Buried Channel ◽  
Operation Characteristics

Operation characteristics of Poly-Si nanowire charge-trapping flash memory devices with SiGe and Ge buried channels

Vacuum ◽  
2017 ◽  
Vol 140 ◽  
pp. 53-57 ◽  
Author(s):  
Hsin-Kai Fang ◽  
Kuei-Shu Chang-Liao ◽  
Chien-Pang Huang ◽  
Wei-Zhi Lee
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Devices ◽  
Si Nanowire ◽  
Buried Channels ◽  
Operation Characteristics

Improvement on programming and erasing speeds for charge-trapping flash memory device with SiGe buried channel

2010 ◽  
Vol 54 (10) ◽  
pp. 1113-1118 ◽  
Author(s):  
Li-Jung Liu ◽  
Kuei-Shu Chang-Liao ◽  
Wen-Chun Keng ◽  
Tien-Ko Wang
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Buried Channel

scholarly journals Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory

Nanomaterials ◽  
2018 ◽  
Vol 8 (10) ◽  
pp. 799 ◽  
Author(s):  
Jer Wang ◽  
Chyuan Kao ◽  
Chien Wu ◽  
Chun Lin ◽  
Chih Lin
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Dielectric Constants ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Hysteresis Curve ◽  
Band Shift ◽  
K Value ◽  
High K

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.

scholarly journals Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device

2016 ◽  
Vol 2016 ◽  
pp. 1-6 ◽  
Author(s):  
W. J. Liu ◽  
L. Chen ◽  
P. Zhou ◽  
Q. Q. Sun ◽  
H. L. Lu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Room Temperature ◽  
Metal Layer ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Memory Device ◽  
Water Molecules ◽  
Oh Groups ◽  
Chemical Vapor Deposited ◽  
A Charge

We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.

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