Fast Acquisition Clock and Data Recovery Circuit With Low Jitter

2006 ◽  
Vol 41 (5) ◽  
pp. 1016-1024 ◽  
Author(s):  
R. Zhang ◽  
G.S. La Rue
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Fast Acquisition ◽  
Low Jitter

Low-jitter design method based on n-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

2009 ◽  
Vol 45 (16) ◽  
pp. 808 ◽  
Author(s):  
K. Kishine ◽  
H. Inaba ◽  
Ma. Nakamura ◽  
Mi. Nakamura ◽  
Y. Ohtomo ◽  
...  
Keyword(s):  
Design Method ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Low Jitter

scholarly journals 2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator

2006 ◽  
Vol 4 ◽  
pp. 287-291
Author(s):  
S. Tontisirin ◽  
R. Tielert
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Data Recovery ◽  
Voltage Controlled Oscillator ◽  
Clock Generator ◽  
Low Jitter ◽  
Phase Clock ◽  
Multi Phase ◽  
Frequency Detector

Abstract. A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm2 and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1–2.25 Gb/s. Measurement of Bit-Error Rate is less than 10−12 for 2.25 Gb/s incoming data 27−1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz.

scholarly journals A low jitter clock and data recovery with a single edge sensing Bang-Bang PD

2014 ◽  
Vol 11 (7) ◽  
pp. 20140088-20140088
Author(s):  
Taek-Joon Ahn ◽  
Sang-Soon Im ◽  
Yong-Sung Ahn ◽  
Jin-Ku Kang
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Single Edge ◽  
Low Jitter
Sign in / Sign up

Export Citation Format

Share Document