Low-jitter design method based on n-domain jitter analysis for 10 Gbit/s clock and data recovery ICs
2016 ◽
Vol 45
(6)
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pp. 851-858
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Keyword(s):
2004 ◽
Vol 51
(12)
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pp. 2356-2364
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2006 ◽
Vol 41
(5)
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pp. 1016-1024
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