Polymer thick film (PTF) and flex technologies for low cost power electronics packaging

2002 ◽  
Author(s):  
A.B. Lostetter ◽  
F. Barlow ◽  
A. Elshabini ◽  
K. Olejniczak ◽  
S. Ang
Keyword(s):  
Power Electronics ◽  
Thick Film ◽  
Low Cost ◽  
Electronics Packaging

Advanced DBC - Highly Reliable and Conductive Copper Ceramic Substrates

2016 ◽  
Vol 2016 (CICMT) ◽  
pp. 000073-000078
Author(s):  
Paul Gundel ◽  
Anton Miric ◽  
Kai Herbst ◽  
Melanie Bawohl ◽  
Jessica Reitz ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Thermal Cycling ◽  
Power Electronics ◽  
Thick Film ◽  
Low Cost ◽  
Automotive Applications ◽  
Ceramic Substrates ◽  
Hybrid Technologies

Abstract So far Direct Bonded Copper (DBC) substrates have been the standard for power electronics. They provide excellent electrical and thermal conductivity at low cost. Weaknesses of DBC technology are the inevitable warpage and the relatively low reliability under thermal cycling. The low reliability poses a significant hurdle in particular for automotive applications with high lifetime requirements. Thick Print Copper (TPC) substrates with low warpage and excellent reliability overcome these weaknesses, but also provide a reduced conductivity at a higher cost. We present two thick-film/DBC hybrid technologies which combine the best properties of DBC and TPC: excellent conductivity, low cost, reduced warpage and excellent reliability.

A reliable low cost power electronics interface for photovoltaic energy systems

Solar Energy ◽  
2014 ◽  
Vol 108 ◽  
pp. 370-376 ◽  
Author(s):  
Wajiha Shireen ◽  
Adarsh Nagarajan ◽  
Sonal Patel ◽  
Radhakrishna Kotti ◽  
Preetham Goli
Keyword(s):  
Power Electronics ◽  
Low Cost ◽  
Energy Systems ◽  
Photovoltaic Energy

scholarly journals Tailoring the Crystallographic Texture and Electrical Properties of Inkjet-printed Interconnects for Use in Microelectronics

2011 ◽  
Vol 1335 ◽  
Author(s):  
Romain Cauchois ◽  
Mohamed Saadaoui ◽  
Karim Inal ◽  
Beatrice Dubois-Bonvalot ◽  
Jean-Christophe Fidalgo
Keyword(s):  
Low Cost ◽  
Gold Wire ◽  
Electronics Packaging ◽  
Fiber Texture ◽  
Bonding Process ◽  
Process Step ◽  
Gold Thin Film ◽  
Microelectronic Devices ◽  
Electrical Interconnects ◽  
Sintering Condition

ABSTRACTIn this paper, silver nanoparticles with a mean diameter of 40 nm are studied for future applications in microelectronic devices. The enhanced diffusivity of nanoparticles is exploited to fabricate electrical interconnects at low temperature. Sintering condition has been tuned to tailor the grain size so that electrical resistivity can be lowered down to 3.4 μOhm∙cm. In this study, a {111}-textured gold thin film has been used to increase diffusion routes. The combined effects of the substrate crystalline orientation and the sintering condition have been demonstrated to have a significant impact on microstructures. In particular, a {111} fiber texture is developed above 300°C in printed silver only if the underlying film exhibits a preferential orientation. This condition appeared as essential for the efficiency of the gold wire-bonding process step. Thus, inkjet-printed interconnects show a prospective potential compared to conventional subtractive technique and offers new opportunities for low cost metallization in electronics packaging.

Flipchip Bonding of Si Chip on Flexible PEN Foil using Novel Electronic 100 μm Pitch Fan-out Circuitry

2007 ◽  
Vol 1030 ◽  
Author(s):  
Jeroen van den Brand ◽  
Erik Veninga ◽  
Roel Kusters ◽  
Tomas Podprocky ◽  
Andreas Dietzel
Keyword(s):  
Thick Film ◽  
Low Cost ◽  
Cost Effective ◽  
High Density ◽  
Polyethylene Naphthalate ◽  
Electronic Circuitry ◽  
Effective Technology

AbstractA novel, cost effective technology to manufacture high density embedded electronic circuitry is demonstrated. The process consists of laser photoablation of the circuitry into a substrate through a mask and subsequent filling using a polymer thick film paste. Because the volume of the substrate is used it is possible to make thick and thereby highly conductive lines using low cost materials and processes. The process is demonstrated for a fan out circuitry in 100 µm thick polyethylene naphthalate (PEN). The fan out circuitry has linewidths of 50 µm and line spacings of 100 µm. The usability of the circuitry is demonstrated by the successful flipchip bonding of a thinned Si daisy chain dummy chip with 176 IO's.

Microgrid Model on Homer Software

2021 ◽  
Vol 9 (VI) ◽  
pp. 757-760
Author(s):  
Mohd Ahamad
Keyword(s):  
Power Generation ◽  
Power Electronics ◽  
Life Cycle Cost ◽  
Low Voltage ◽  
High Reliability ◽  
Low Cost ◽  
Local Area ◽  
New Paradigm ◽  
Power Sources ◽  
Wide Range

A new concept in power generation is a microgrid. The Microgrid concept assumes a cluster of loads and microsources operating as a single controllable system that provides power to its local area. This concept provides a new paradigm for defining the operation of distributed generation. The microsources of special interest for MGs are small (<100-kW) units with power electronic interfaces. These sources are placed at customers sites. They are low cost, low voltage and have a high reliability with few emissions. Power electronics provide the control and flexibility required by the MG concept. A properly designed power electronics and controllers insure that the MG can meet the needs of its customers as well as the utilities. The goal of this project is to build a complete model of Microgrid including the power sources, their power electronics, and a load and mains model in THE HOMER. The HOMER Micropower Optimization Model is a computer model developed by the U.S. National Renewable Energy Laboratory (NREL) to assist in the design of micropower systems and to facilitate the comparison of power generation technologies across a wide range of applications. HOMER models a power system’s physical behavior and its life-cycle cost, which is the total cost of installing and operating the system over its life span. HOMER allows the modeler to compare many different design options based on their technical and economic merits. It also assists in understanding and quantifying the effects of uncertainty or changes in the inputs.

Die-Attach Bonding with Etched Micro Brass Metal Pigment Flakes for High-Power Electronics Packaging

2021 ◽  
Author(s):  
Sri Krishna Bhogaraju ◽  
Hiren R. Kotadia ◽  
Fosca Conti ◽  
Armin Mauser ◽  
Thomas Rubenbauer ◽  
...  
Keyword(s):  
Power Electronics ◽  
High Power ◽  
Electronics Packaging ◽  
Die Attach

Chemical selective coating of nickel / palladium / gold metallization on screen-printed thick film on LTCC and Al2O3 ceramic for high temperature applications

2012 ◽  
Vol 2012 (CICMT) ◽  
pp. 000334-000338
Author(s):  
Jens Müller ◽  
Thomas Mache ◽  
Torsten Thelemann
Keyword(s):  
High Temperature ◽  
Thick Film ◽  
Low Cost ◽  
Gold Wire ◽  
Wire Bonding ◽  
Pure Gold ◽  
Al2o3 Ceramic ◽  
Selective Coating ◽  
Silver Palladium ◽  
Silver Silver

Electroless plating on silver is a low cost alternative to printing of mixed metals or pure gold paste systems on LTCC. It overcomes the necessity to have material transitions from inner to outer layers or from conductor lines to wire bonding- or solder-pads. Since no commercial process and material set for silver thick film conductors has been available on the market a proprietary Ni/Pd/Au coating technology was developed for the use on silver inks for LTCC and Al2O3-ceramic as a base for both soldering and wire bonding. The work included the screening of different chemicals as well as several silver paste systems from two commercial vendors. Conductor adhesion, plating layer thicknesses, plating accuracy, (lead free) solderability and gold wire-bondability were assessed to optimize the process. Layers of about 5 microns Ni, (0.1 to 0.3) microns Pd and (0.05 to 0.15) microns Au were electrolessly deposited. The developed Ni-Pd-Au finish is an economical alternative with only about a quarter of the cost compared to the conventional use of silver, silver / palladium and gold compounds for ceramic substrates. This technology allows coating of the structures down to a fine pad size of 200×200 microns and a minimum line width of 100 microns, without reducing the adhesion mechanism between thick-film metallization and ceramic substrate. By covering of pure conductors with high temperature glass or dielectrics, further material saving is possible. Besides, the process offers also very good coating of structures in cavities.

Design of TSV-based Inductors for Internet of Things

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 002111-002130 ◽  
Author(s):  
Bruce C Kim ◽  
Saikat Mondal
Keyword(s):  
Magnetic Field ◽  
Internet Of Things ◽  
Power Electronics ◽  
Eddy Current ◽  
Electronics Packaging ◽  
High Density ◽  
Metal Core ◽  
The Core ◽  
Iot Applications ◽  
The Magnetic Field

This paper describes the design of a Through Silicon Via based high density 3D inductors for Internet of Things (IoT) applications. We present some possible challenges for TSV-based inductors in IoT applications. The current trend towards Internet of Things (IOT), System in Package (SiP) and Package-on-Package (PoP) requires meeting the power requirements of heterogeneous technologies while maintaining minimum package size. 3-D chip stacking has emerged as one of the potential solutions due to its high density integration in a 3D power electronics packaging regime. As an integral part of many power electronics applications, TSV-based inductors are becoming a popular choice because of their high inductance density due to the reduced on-chip footprint compared to conventional planar inductors. Depending on the requirement, values of these inductors could range from a few nanohenries to hundreds of microhenries. Small inductors with a high quality factor are mainly used for RF filter applications, whereas large inductors are used in power electronics packaging. For high inductance it is necessary to use ferromagnetic materials. A conventional ferromagnetic metal core like nickel could offer high permeability, which can help to boost the inductance. However, the magnetic field lines within a metal core induce eddy current which can have multiple adverse effect in power electronics packaging. For example, it has long been known that the current can increase the resistance in transformer winding [1]. Eddy current can also heat up the core of the inductor which makes the heat sink process in 3D packaging even more challenging. One way to decrease the eddy current, is to pattern and laminate the core block into multiple segments orthogonal to the direction of the magnetic field line [2]. Another method is to increase the resistivity of the core material so that the eddy current is limited to a very small magnitude [3].

Sign in / Sign up

Export Citation Format

Share Document