Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems

2007 ◽  
Author(s):  
Roman Lysecky
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
High Performance ◽  
Power Efficient

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems

2016 ◽  
Vol 65 (7) ◽  
pp. 2313-2324 ◽  
Author(s):  
Keni Qiu ◽  
Qingan Li ◽  
Jingtong Hu ◽  
Weigong Zhang ◽  
Chun Jason Xue
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
High Performance ◽  
Loop Tiling

scholarly journals A Power Efficient Improved NOR-Type TCAM Design using OR-Type Match-Line Segment

2020 ◽  
Vol 8 (6) ◽  
pp. 4885-4890
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Cmos Technology ◽  
The Novel ◽  
Metal Gate ◽  
Power Efficient ◽  
Content Addressable Memory ◽  
Ternary Content Addressable Memory ◽  
High K

This paper presents the novel way to deal with diminish power utilization in a ternary content addressable memory (TCAM) designed in current innovation. The main aim of this TCAM design is to reduce the dynamic power consumption. In TCAM large amount of the power consumption happens during search operation, so we focussed on this area. Here right now give pragmatic plan of a TCAM which is arranged for low-power applications. Simulation of this design has done in Tanned EDA V.16 tool. For simulations of Low power TCAM designs we used predictive technology model (PTM) 45nm for high-performance applications which include metal gate, high-k and stress impact of CMOS technology.

SH-X3 xible SuperH multi-core for high-performance and low-power embedded systems

2007 ◽  
Author(s):  
Shinichi Shibahara ◽  
Masashi Takada ◽  
Tatsuya Kamei ◽  
Kiyoshi Hayase ◽  
Yutaka Yoshida ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
High Performance

Write Mode Aware Loop Tiling for High-Performance Low-Power Volatile PCM in Embedded Systems

2020 ◽  
pp. 171-198
Author(s):  
Keni Qiu ◽  
Qingan Li ◽  
Jingtong Hu ◽  
Weigong Zhang ◽  
Chun Jason Xue
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
High Performance ◽  
Loop Tiling
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