Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization

2005 ◽  
Author(s):  
Rahul Rao ◽  
K. Agarwal ◽  
A. Devgan ◽  
K. Nowka ◽  
D. Sylvester ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Yield Analysis ◽  
Parametric Yield

Local Supply Voltage Adjustment for Low Power Parametric Yield Increase

2006 ◽  
Author(s):  
Matthias Eireiner ◽  
Stephan Henzler ◽  
Georg Georgakos ◽  
Joerg Berthold ◽  
Doris Schmitt-Landsiedel
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Yield Increase ◽  
Parametric Yield ◽  
Local Supply

Parametric yield analysis on FEM based microsystem designs

2007 ◽  
Author(s):  
Shyam Praveen Vudathu ◽  
Umamaheswara Reddy Vemulapati ◽  
Duane Boning ◽  
Vasudevarao Ramanolla ◽  
Rainer Laur ◽  
...  
Keyword(s):  
Yield Analysis ◽  
Parametric Yield

scholarly journals Modelling of the parametric yield in decananometer SRAM-Arrays

2006 ◽  
Vol 4 ◽  
pp. 281-285 ◽  
Author(s):  
Th. Fischer ◽  
T. Nirschl ◽  
B. Lemaitre ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Simulations ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Optimal Solution ◽  
Global Scale ◽  
The Other ◽  
Specific Product ◽  
Low Leakage ◽  
Parametric Yield

Abstract. In today's decananometer (90 nm, 65 nm, ...), CMOS technologies variations of device parameters play an ever more important role. Due to the demand for low leakage systems, supply voltage is decreased on one hand and the transistor threshold voltage is increased on the other hand. This reduces the overdrive voltage of the transistors and leads to decreasing read and write security margins in static memories (SRAM). In addition, smaller dimensions of the devices lead to increasing variations of the device parameters, thus mismatch effects increase. It can be shown that local variations of the transistor parameters limit the functionality of circuits stronger than variations on a global scale or hard defects. We show a method to predict the yield for a large number of SRAM devices without time consuming Monte Carlo simulations in dependence of various parameters (Vdd, temperature, technology options, transistor dimensions, ...). This helps the designer to predict the yield for various system options and transistor dimensions, to choose the optimal solution for a specific product.

Parametric Yield Analysis and Optimization in Leakage Dominated Technologies

2007 ◽  
Vol 15 (6) ◽  
pp. 613-623 ◽  
Author(s):  
K. Agarwal ◽  
R. Rao ◽  
D. Sylvester ◽  
R. Brown
Keyword(s):  
Yield Analysis ◽  
Parametric Yield

Building an infrastructure for parametric yield analysis: concept and implementation of a DFM platform (Invited Paper)

2005 ◽  
Author(s):  
John Gookassian ◽  
Bob Pack ◽  
Mitch Heins ◽  
John Garcia ◽  
Hitendra Divecha ◽  
...  
Keyword(s):  
Yield Analysis ◽  
Parametric Yield ◽  
Analysis Concept
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