Power-Efficient Continuous-Flow Memory-Based FFT Processor for WiMax OFDM Mode

2006 ◽  
Author(s):  
Pei-Yun Tsai ◽  
Tsung-Hsueh Lee ◽  
Tzi-Dar Chiueh
Keyword(s):  
Continuous Flow ◽  
Power Efficient ◽  
Fft Processor

A Low-Cost Continuous-Flow Parallel Memory-Based FFT Processor for UWB Applications

2011 ◽  
Vol E94-A (1) ◽  
pp. 315-323 ◽  
Author(s):  
Chin-Long WEY ◽  
Shin-Yo LIN ◽  
Hsu-Sheng WANG ◽  
Hung-Lieh CHEN ◽  
Chun-Ming HUANG
Keyword(s):  
Continuous Flow ◽  
Low Cost ◽  
Parallel Memory ◽  
Fft Processor ◽  
Uwb Applications

scholarly journals Double Precision Floating Point Fft Processor using Vedic Mathematics

2019 ◽  
Vol 8 (4) ◽  
pp. 8533-8538
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Vedic Mathematics ◽  
Communication Signal ◽  
Fft Processor ◽  
Complex Multiplications ◽  
Point Fast Fourier Transform

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

scholarly journals A Novel Address Scheme for Continuous-Flow Parallel Memory-Based Real-Valued FFT Processor

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 1042 ◽  
Author(s):  
Min Yuan ◽  
Zhenguo Ma ◽  
Feng Yu ◽  
Qianjian Xing
Keyword(s):  
Fourier Transform ◽  
Parallel Processing ◽  
Continuous Flow ◽  
State Of The Art ◽  
Signal Flow Graph ◽  
Normal Order ◽  
Variable Size ◽  
Flow Graph ◽  
Parallel Memory ◽  
Fft Processor

In this article, we present a modified constant-geometry based signal flow graph for memory-based real-valued fast Fourier transform architecture. Without an extra permutation, the corresponding address scheme solves the memory conflict and achieves continuous-flow operation with the minimal memory and computation cycles requirement when compared to the state-of-the-art designs. Besides, the address scheme meets the constraint of in-place operation, concurrent I/O, normal-order I/O, variable size, and parallel processing. The experimental results demonstrate the resource and frequency efficiency of the proposed address scheme.

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