scholarly journals A Novel Address Scheme for Continuous-Flow Parallel Memory-Based Real-Valued FFT Processor

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 1042 ◽  
Author(s):  
Min Yuan ◽  
Zhenguo Ma ◽  
Feng Yu ◽  
Qianjian Xing
Keyword(s):  
Fourier Transform ◽  
Parallel Processing ◽  
Continuous Flow ◽  
State Of The Art ◽  
Signal Flow Graph ◽  
Normal Order ◽  
Variable Size ◽  
Flow Graph ◽  
Parallel Memory ◽  
Fft Processor

In this article, we present a modified constant-geometry based signal flow graph for memory-based real-valued fast Fourier transform architecture. Without an extra permutation, the corresponding address scheme solves the memory conflict and achieves continuous-flow operation with the minimal memory and computation cycles requirement when compared to the state-of-the-art designs. Besides, the address scheme meets the constraint of in-place operation, concurrent I/O, normal-order I/O, variable size, and parallel processing. The experimental results demonstrate the resource and frequency efficiency of the proposed address scheme.

A Low-Cost Continuous-Flow Parallel Memory-Based FFT Processor for UWB Applications

2011 ◽  
Vol E94-A (1) ◽  
pp. 315-323 ◽  
Author(s):  
Chin-Long WEY ◽  
Shin-Yo LIN ◽  
Hsu-Sheng WANG ◽  
Hung-Lieh CHEN ◽  
Chun-Ming HUANG
Keyword(s):  
Continuous Flow ◽  
Low Cost ◽  
Parallel Memory ◽  
Fft Processor ◽  
Uwb Applications

scholarly journals Erratum: A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes [IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170660]

2017 ◽  
Vol 14 (22) ◽  
pp. 20178005-20178005
Author(s):  
Yinghui Tian ◽  
Yong Hei ◽  
Zhizhe Liu ◽  
Zhixiong Di ◽  
Qi Shen ◽  
...  
Keyword(s):  
Signal Flow Graph ◽  
Flow Graph ◽  
Signal Flow ◽  
Fft Processor

scholarly journals Radix-2α/4β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-13 ◽  
Author(s):  
Marwan A. Jaber ◽  
Daniel Massicotte
Keyword(s):  
Fourier Transform ◽  
Parallel Processing ◽  
Fast Fourier Transform ◽  
Critical Path ◽  
Building Blocks ◽  
Circuit Diagram ◽  
Fft Processor ◽  
Building Process ◽  
Complex Multiplier

This paper describes an embedded FFT processor where the higher radices butterflies maintain one complex multiplier in its critical path. Based on the concept of a radix-r fast Fourier factorization and based on the FFT parallel processing, we introduce a new concept of a radix-r Fast Fourier Transform in which the concept of the radix-r butterfly computation has been formulated as the combination of radix-2α/4β butterflies implemented in parallel. By doing so, the VLSI butterfly implementation for higher radices would be feasible since it maintains approximately the same complexity of the radix-2/4 butterfly which is obtained by block building of the radix-2/4 modules. The block building process is achieved by duplicating the block circuit diagram of the radix-2/4 module that is materialized by means of a feed-back network which will reuse the block circuit diagram of the radix-2/4 module.

A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design

2019 ◽  
Vol 66 (1) ◽  
pp. 106-110 ◽  
Author(s):  
Yinghui Tian ◽  
Yong Hei ◽  
Zhizhe Liu ◽  
Qi Shen ◽  
Zhixiong Di ◽  
...  
Keyword(s):  
Processor Design ◽  
Signal Flow Graph ◽  
Flow Graph ◽  
Signal Flow ◽  
Fft Processor

scholarly journals A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes

2017 ◽  
Vol 14 (15) ◽  
pp. 20170660-20170660
Author(s):  
Yinghui Tian ◽  
Yong Hei ◽  
Zhizhe Liu ◽  
Zhixiong Di ◽  
Qi Shen ◽  
...  
Keyword(s):  
Signal Flow Graph ◽  
Flow Graph ◽  
Signal Flow ◽  
Fft Processor

scholarly journals A 2048-point Split-Radix Fast Fourier Transform Computed using Radix-4 Butterfly Units

2019 ◽  
Vol 8 (4) ◽  
pp. 2043-2046
Keyword(s):  
Fourier Transform ◽  
Power Consumption ◽  
Low Power ◽  
Fast Fourier Transform ◽  
Fourier Transforms ◽  
Low Power Consumption ◽  
Signal Flow Graph ◽  
Flow Graph ◽  
Dynamic Power ◽  
Fft Algorithms

For the low-power consumption of fast fourier transform, Split-radix fast Fourier transforms are widely used. SRFFT uses less number of mathematical calculations amongst the different FFT algorithms. Split-radix FFT has the same signal flow graph that of conventional radix-2/4 FFT’s. Therefore, the address generation method is same for SRFFT as of radix-2. A low power SRFFT architecture with modified butterfly units is presented over here. Here, it is shown that the, a 2048-point SRFFT is computed using radix-4 butterfly unist. Dynamic power is saved, on compromising the use of extra hardware. Here, the architecture size is increased from radix-2 to 4 and the dynamic power consumption is evaluated.

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