EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems

2014 ◽  
Author(s):  
Lars Schor ◽  
Iuliana Bacivarov ◽  
Luis Gabriel Murillo ◽  
Pier Stanislao Paolucci ◽  
Frederic Rousseau ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Design Flow ◽  
Flow Dynamic ◽  
Tile Systems

scholarly journals Fault-tolerant ASIC: Design and implementation

2013 ◽  
Vol 26 (3) ◽  
pp. 175-186 ◽  
Author(s):  
Z. Stamenkovic ◽  
V. Petrovic ◽  
G. Schoof
Keyword(s):  
Fault Tolerant ◽  
Logic Synthesis ◽  
Design Flow ◽  
Single Event ◽  
Asic Design ◽  
Single Event Upsets ◽  
Design And Implementation ◽  
Standard Design ◽  
Extra Step ◽  
Definition Of

The paper presents fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for a modified fault-tolerant ASIC design flow. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the redundant power domains and placement of the SPS) have to be performed in the layout phase. The concept has been proven by design and implementation of the two digital circuits: shift-register and synchronous counter.

scholarly journals Isolation Design Flow Effectiveness Evaluation Methodology for Zynq SoCs

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 814
Author(s):  
Arsalan Ali Malik ◽  
Anees Ullah ◽  
Ali Zahir ◽  
Affaq Qamar ◽  
Shadan Khan Khattak ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Fault Injection ◽  
Random Access ◽  
Evaluation Process ◽  
Design Flow ◽  
Evaluation Methodology ◽  
Single Chip ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Technology Nodes

Static Random-Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) are increasingly being used in many application domains due to their higher logic density and reconfiguration capabilities. However, with state-of-the-art FPGAs being manufactured in the latest technology nodes, reliability is becoming an important issue, particularly for safety-critical avionics, automotive, aerospace, industrial robotics, medical, and financial systems. Therefore, fault tolerant system design methodologies have become essential in the aforementioned application domains. The Isolation Design Flow (IDF) is one such design methodology that has promising prospects due to its ability to isolate logic design modules at the physical level for fault containment purposes. This paper proposes a methodology to evaluate the effectiveness of the IDF. To do so, reverse engineering is used to enable fault injection on the IDF designs with minimal changes in the bit-stream. This reduces the time needed to inject a fault significantly thus accelerating the evaluation process. Then this methodology is applied to a case study of a single-chip cryptography application on a ZynQ SoC. Specifically, an Advanced Encryption Standard (AES) Duplication With Comparison (DWC) design is physically isolated with IDF and subsequently subjected to frame-level Fault Injection (FI) in the configuration memory.

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