A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's

2008 ◽  
Author(s):  
Luca Sterpone ◽  
Niccolo' Battezzati
Keyword(s):  
Performance Optimization ◽  
Fault Tolerant ◽  
Design Flow ◽  
Novel Design

The Optimal Checkpoint Interval for the Long-Running Application

2021 ◽  
pp. 2590-2599
Author(s):  
Yongning Zhai ◽  
Weiwei Li
Keyword(s):  
Distributed Computing ◽  
Performance Optimization ◽  
Fault Tolerant ◽  
Computing System ◽  
Effective Rate ◽  
Performance Degradation ◽  
Numerical Results ◽  
Failure Distribution ◽  
Overhead Ratio

For the distributed computing system, excessive or deficient checkpointing operations would result in severe performance degradation. To minimize the expected computation execution of the long-running application with a general failure distribution, the optimal equidistant checkpoint interval for fault tolerant performance optimization is analyzed and derived in this paper. More precisely, the optimal checkpointing period to determine the proper checkpoint sequence is proposed, and the derivation of the expected effective rate of the defined computation cycle is introduced. Corresponding to the maximal expected effective rate, the constraint of the optimal checkpoint sequence can be obtained. From the constraint of optimality, the optimal equidistant checkpoint interval can be obtained according to the minimal fault tolerant overhead ratio. By the numerical results, the proposal is practical to determine a proper equidistant checkpoint interval for fault tolerant performance optimization.

scholarly journals A Novel Design Flow for Dummy Fill Using Boolean Mask Operations

2012 ◽  
Vol 25 (3) ◽  
pp. 468-479 ◽  
Author(s):  
Tseng-Chin Luo ◽  
Mango C.-T Chao ◽  
P. A. Fisher ◽  
Chun-Ren Kuo
Keyword(s):  
Design Flow ◽  
Novel Design

scholarly journals Novel Design for Quantum Dots Cellular Automata to Obtain Fault-Tolerant Majority Gate

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Razieh Farazkish ◽  
Samira Sayedsalehi ◽  
Keivan Navi
Keyword(s):  
Fault Tolerance ◽  
Cellular Automata ◽  
Fault Tolerant ◽  
Electrostatic Energy ◽  
Majority Gate ◽  
Quantum Dot Cellular Automata ◽  
Dislocation Cells ◽  
The Difference ◽  
Qca Circuits ◽  
Novel Design

Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at nanoscale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states) and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.

scholarly journals Fault-tolerant ASIC: Design and implementation

2013 ◽  
Vol 26 (3) ◽  
pp. 175-186 ◽  
Author(s):  
Z. Stamenkovic ◽  
V. Petrovic ◽  
G. Schoof
Keyword(s):  
Fault Tolerant ◽  
Logic Synthesis ◽  
Design Flow ◽  
Single Event ◽  
Asic Design ◽  
Single Event Upsets ◽  
Design And Implementation ◽  
Standard Design ◽  
Extra Step ◽  
Definition Of

The paper presents fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for a modified fault-tolerant ASIC design flow. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the redundant power domains and placement of the SPS) have to be performed in the layout phase. The concept has been proven by design and implementation of the two digital circuits: shift-register and synchronous counter.

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