New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design

2006 ◽  
Author(s):  
Eun-Ju Choi ◽  
Kyoung-Rok Cho ◽  
Je-Hoon Lee
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Asynchronous Circuit ◽  
Data Encoding ◽  
Encoding Method ◽  
Asynchronous Circuit Design

Recent Advances in Low Power Asynchronous Circuit Design

2017 ◽  
Vol 13 (3) ◽  
pp. 280-297 ◽  
Author(s):  
Jia Di ◽  
Brent A. Bell ◽  
William Bouillon ◽  
John Brady ◽  
Thao Le ◽  
...  
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Asynchronous Circuit ◽  
Recent Advances ◽  
Asynchronous Circuit Design

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

2008 ◽  
Vol 4 (3) ◽  
pp. 337-348 ◽  
Author(s):  
Andrew Bailey ◽  
Ahmad Al Zahrani ◽  
Guoyuan Fu ◽  
Jia Di ◽  
Scott Smith
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Asynchronous Circuit ◽  
Ultra Low Power ◽  
Asynchronous Circuit Design

scholarly journals Low power circuit design using NCL based asynchronous method

2021 ◽  
Vol 22 (3) ◽  
pp. 1284
Author(s):  
Toi Le Thanh ◽  
Lac Truong Tri ◽  
Trang Hoang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Electromagnetic Interference ◽  
Design Model ◽  
Design Technique ◽  
Asynchronous Circuit ◽  
Clock Gating ◽  
Power Circuit ◽  
Asynchronous Circuit Design

The null convention logic (NCL) based circuit design methodology eliminates the problems related to noise, clock tree, electromagnetic interference and also reduces significant power consumption. In this paper, we would like to demonstrate the advantage of low power consumption of the NCL based asynchronous circuit design on a large design scale, thus we used the advanced encryption standard (AES) encryption design as an illustrative example. In addition, we also proposed two pipelined AES encryption models using the synchronous circuit design technique and the asynchronous circuit design technique based on NCL. Besides, these two models were realized by using version control system (VCS) tool to simulate and Design Compiler tool to synthesize parameters in power consumption, processing speed and area. The synthesis results of these two models indicated that power consumption of the NCL based asynchronous AES encryption model had a decrease of 71% compared with the synchronous AES encryption model. Moreover, we show the outstanding advantage of the power consumption of the NCL based asynchronous design model (a decrease of 91.12% and 93,23%) compared to the synchronous design model using clock gating technique and without using clock gating technique respectively.

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