High-Performance 100Gb/s DWDM Transmitter through Fully Passive Assembly of a Single-Chip Array of Directly Modulated Lasers with a SiO2 AWG

2014 ◽  
Author(s):  
H. Debregeas ◽  
C. Ferrari ◽  
A.R. Papazian ◽  
M. Cappuzzo ◽  
F. Klemens ◽  
...  
Keyword(s):  
High Performance ◽  
Single Chip ◽  
Directly Modulated Lasers

Package Voltage Regulators: The Answer for Power Management Challenges

2019 ◽  
Vol 2019 (1) ◽  
pp. 000438-000443 ◽  
Author(s):  
Joseph Meyer ◽  
Reza Moghimi ◽  
Noah Sturcken
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Power Conversion ◽  
Cmos Technology ◽  
Voltage Regulation ◽  
Voltage Regulators ◽  
Electronic Systems ◽  
Single Chip ◽  
Fully Integrated ◽  
Computational Performance

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

High Precision Ultrasonic Ranging System for Mobile Robot Navigation

2012 ◽  
Vol 249-250 ◽  
pp. 1139-1143
Author(s):  
Yan Gao ◽  
Li Na Jia ◽  
Bo Wang ◽  
Li Hua Liu ◽  
Li Ming Huang
Keyword(s):  
Mobile Robot ◽  
High Precision ◽  
High Performance ◽  
Mobile Robot Navigation ◽  
Peak Time ◽  
Single Chip ◽  
Single Chip Microcomputer ◽  
Detection Point ◽  
Environment Temperature ◽  
Ultrasonic Ranging

This paper introduces ultrasonic ranging system which can be applied to avoid obstacle and navigate for mobile robot .This system is composed of AT89S51 single chip microcomputer ,ultrasonic transmitting circuit, ultrasonic receiving circuit, amplifying and filtering circuit , peak value time detecting circuit, environment temperature compensation circuit. The method of echo peak time detection point is used to eliminate the error. It is proved that The maximum range of the system is 10 meter and maximum measurement error can be controlled to± 2 cm or so. This system has such merits as rapid corresponding, high precision, high performance price rate.

A High Performance Single Chip LSI for Error Correction of Optical Disk Memory

1989 ◽  
Vol 28 (S3) ◽  
pp. 315
Author(s):  
Katsumi Murai ◽  
Makoto Ichinose ◽  
Yuzuru Kuroki ◽  
Makoto Usui ◽  
Yuji Tagaki ◽  
...  
Keyword(s):  
Error Correction ◽  
High Performance ◽  
Optical Disk ◽  
Single Chip ◽  
Disk Memory

scholarly journals The Single Row Routing Problem Revisited: A Solution Based on Genetic Algorithms

VLSI Design ◽  
2002 ◽  
Vol 14 (2) ◽  
pp. 123-141 ◽  
Author(s):  
Albert Y. Zomaya ◽  
Roger Karpin ◽  
Stephan Olariu
Keyword(s):  
Genetic Algorithms ◽  
Computer Aided Design ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Heuristic Algorithms ◽  
Classical Problem ◽  
Vlsi Circuits ◽  
Single Chip ◽  
Routing Problem ◽  
Single Row

With the advent of VLSI technology, circuits with more than one million transistors have been integrated onto a single chip. As the complexity of ICs grows, the time and money spent on designing the circuits become more important. A large, often dominant, part of the cost and time required to design an IC is consumed in the routing operation. The routing of carriers, such as in IC chips and printed circuit boards, is a classical problem in Computer Aided Design. With the complexity inherent in VLSI circuits, high performance routers are necessary. In this paper, a crucial step in the channel routing technique, the single row routing (SRR) problem, is considered. First, we discuss the relevance of SRR in the context of the general routing problem. Secondly, we show that heuristic algorithms are far from solving the general problem. Next, we introduce evolutionary computation, and, in particular, genetic algorithms (GAs) as a justifiable method in solving the SRR problem. Finally, an efficient O (nk) complexity technique based on GAs heuristic is obtained to solve the general SRR problem containing n nodes. Experimental results show that the algorithm is faster and can often generate better results than many of the leading heuristics proposed in the literature.

scholarly journals Implementation of Face Recognition Processing Using an Embedded Processor

2005 ◽  
Vol 17 (4) ◽  
pp. 428-436 ◽  
Author(s):  
Hiroyuki Kondo ◽  
◽  
Masami Nakajima ◽  
Miroslaw Bober ◽  
Krzysztof Kucharski ◽  
...  
Keyword(s):  
Face Recognition ◽  
Power Consumption ◽  
High Performance ◽  
Supply Voltage ◽  
Chip Multiprocessor ◽  
Low Power Consumption ◽  
Single Chip ◽  
Power Supply Voltage ◽  
Embedded Processor ◽  
Tremendous Amount

Embedded processors are conventionally difficult to use in face recognition in the security and robotic fields because of the tremendous amount of processing required. We implemented face recognition processing with a multicore based embedded processor having low power consumption and high performance. The single-chip multiprocessor is manufactured using a 0.15μm process with two M32R cores, 512KB of SRAM, and peripheral circuits integrated on a single-chip. It has a power supply voltage of 1.5V, a frequency of 600MHz, and power consumption of 800mW.

scholarly journals Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

2021 ◽  
Author(s):  
Isiaka A. Alimi ◽  
Romil K. Patel ◽  
Oluyomi Aboderin ◽  
Abdelgader M. Abdalla ◽  
Ramoni A. Gbadamosi ◽  
...  
Keyword(s):  
High Performance ◽  
Research Direction ◽  
Network On Chip ◽  
Limiting Factor ◽  
Single Chip ◽  
Chip Design ◽  
Application Mapping ◽  
Technology Advancement ◽  
On Chip ◽  
Heterogeneous Cores

Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

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