Parallelization of High-Performance Video Encoding on a Single-Chip Multiprocessor

2007 ◽  
Author(s):  
Di Wu ◽  
Boonshyang Lim ◽  
Johan Eilert ◽  
Dake Liu
Keyword(s):  
High Performance ◽  
Video Encoding ◽  
Chip Multiprocessor ◽  
Single Chip

scholarly journals Implementation of Face Recognition Processing Using an Embedded Processor

2005 ◽  
Vol 17 (4) ◽  
pp. 428-436 ◽  
Author(s):  
Hiroyuki Kondo ◽  
◽  
Masami Nakajima ◽  
Miroslaw Bober ◽  
Krzysztof Kucharski ◽  
...  
Keyword(s):  
Face Recognition ◽  
Power Consumption ◽  
High Performance ◽  
Supply Voltage ◽  
Chip Multiprocessor ◽  
Low Power Consumption ◽  
Single Chip ◽  
Power Supply Voltage ◽  
Embedded Processor ◽  
Tremendous Amount

Embedded processors are conventionally difficult to use in face recognition in the security and robotic fields because of the tremendous amount of processing required. We implemented face recognition processing with a multicore based embedded processor having low power consumption and high performance. The single-chip multiprocessor is manufactured using a 0.15μm process with two M32R cores, 512KB of SRAM, and peripheral circuits integrated on a single-chip. It has a power supply voltage of 1.5V, a frequency of 600MHz, and power consumption of 800mW.

scholarly journals Enhanced multicore–manycore interaction in high-performance video encoding

2018 ◽  
Vol 17 (4) ◽  
pp. 887-902
Author(s):  
Giuliano Grossi ◽  
Pietro Paglierani ◽  
Federico Pedersini ◽  
Alessandro Petrini
Keyword(s):  
High Performance ◽  
Video Encoding

Package Voltage Regulators: The Answer for Power Management Challenges

2019 ◽  
Vol 2019 (1) ◽  
pp. 000438-000443 ◽  
Author(s):  
Joseph Meyer ◽  
Reza Moghimi ◽  
Noah Sturcken
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Power Conversion ◽  
Cmos Technology ◽  
Voltage Regulation ◽  
Voltage Regulators ◽  
Electronic Systems ◽  
Single Chip ◽  
Fully Integrated ◽  
Computational Performance

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

High Precision Ultrasonic Ranging System for Mobile Robot Navigation

2012 ◽  
Vol 249-250 ◽  
pp. 1139-1143
Author(s):  
Yan Gao ◽  
Li Na Jia ◽  
Bo Wang ◽  
Li Hua Liu ◽  
Li Ming Huang
Keyword(s):  
Mobile Robot ◽  
High Precision ◽  
High Performance ◽  
Mobile Robot Navigation ◽  
Peak Time ◽  
Single Chip ◽  
Single Chip Microcomputer ◽  
Detection Point ◽  
Environment Temperature ◽  
Ultrasonic Ranging

This paper introduces ultrasonic ranging system which can be applied to avoid obstacle and navigate for mobile robot .This system is composed of AT89S51 single chip microcomputer ,ultrasonic transmitting circuit, ultrasonic receiving circuit, amplifying and filtering circuit , peak value time detecting circuit, environment temperature compensation circuit. The method of echo peak time detection point is used to eliminate the error. It is proved that The maximum range of the system is 10 meter and maximum measurement error can be controlled to± 2 cm or so. This system has such merits as rapid corresponding, high precision, high performance price rate.

A High Performance Single Chip LSI for Error Correction of Optical Disk Memory

1989 ◽  
Vol 28 (S3) ◽  
pp. 315
Author(s):  
Katsumi Murai ◽  
Makoto Ichinose ◽  
Yuzuru Kuroki ◽  
Makoto Usui ◽  
Yuji Tagaki ◽  
...  
Keyword(s):  
Error Correction ◽  
High Performance ◽  
Optical Disk ◽  
Single Chip ◽  
Disk Memory
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