Equivalence Checking of Bounded Sequential Circuits Based on Gröbner Basis

2014 ◽  
Author(s):  
Guanjun Wang ◽  
Zhao Ying ◽  
Tong Minming
Keyword(s):  
Sequential Circuits ◽  
Equivalence Checking ◽  
Bner Basis

Sequential Circuit Equivalence Checking Method Based on Minimizing Automation

2011 ◽  
Vol 204-210 ◽  
pp. 251-254
Author(s):  
Yu Wan Gu ◽  
Guo Dong Shi ◽  
Shi Yan Xie ◽  
Yu Qiang Sun
Keyword(s):  
Finite State Machine ◽  
State Machine ◽  
Sequential Circuits ◽  
Equivalence Checking ◽  
Sequential Circuit ◽  
Minimization Method ◽  
Finite State ◽  
Graph Form

A parallel checking method is proposed in the paper, in order to improve the speed of sequential circuit checking. The graph form of sequential circuits is isomorphic to finite state machine; a parallel sequential circuit equivalence checking method is designed using parallel minimization method of finite state machine. At last, the effectiveness and feasibility of the method is proved with an instance.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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