Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽

10.3390/sym13040700 ◽

2021 ◽

Vol 13 (4) ◽

pp. 700

Author(s):

Yufei Zhu ◽

Zuocheng Xing ◽

Zerun Li ◽

Yang Zhang ◽

Yifan Hu

Keyword(s):

High Performance ◽

Ldpc Codes ◽

Low Complexity ◽

Cmos Technology ◽

Area Efficiency ◽

Prior Art ◽

New Radio ◽

High Area ◽

Significant Area ◽

Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

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Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2007.891098 ◽

2007 ◽

Vol 15 (1) ◽

pp. 104-114 ◽

Cited By ~ 91

Author(s):

Zhongfeng Wang ◽

Zhiqiang Cui

Keyword(s):

High Speed ◽

Ldpc Codes ◽

Low Complexity ◽

Decoder Design

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An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2014.2368616 ◽

2015 ◽

Vol 62 (3) ◽

pp. 301-305 ◽

Cited By ~ 3

Author(s):

Xin-Ru Lee ◽

Chih-Wen Yang ◽

Chih-Lung Chen ◽

Hsie-Chia Chang ◽

Chen-Yi Lee

Keyword(s):

Ldpc Codes ◽

Stochastic Decoding ◽

Nonbinary Ldpc Codes ◽

Area Efficient

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High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes

Periodica Polytechnica Electrical Engineering and Computer Science ◽

10.3311/ppee.14807 ◽

2019 ◽

Vol 64 (2) ◽

pp. 179-191

Author(s):

Ved Mitra ◽

Mahesh C. Govil ◽

Girdhari Singh ◽

Sanjeev Agrawal

Keyword(s):

Projective Geometry ◽

Critical Path ◽

Ldpc Codes ◽

Cmos Technology ◽

Quantization Scheme ◽

Path Delay ◽

Bit Rate ◽

Error Performance ◽

Ldpc Decoder ◽

Decoder Design

Projective geometry (PG) based low-density parity-check (LDPC) decoder design using iterative sum-product decoding algorithm (SPA) is a big challenge due to higher interconnection and computational complexity, and larger memory requirement caused by relatively higher node degrees. PG-LDPC codes using SPA exhibits the best error performance and faster convergence. This paper presents an efficient novel decoding method, modified SPA (MSPA) that not only shortens the critical-path delay but also improves the hardware utilization and throughput of the decoder while maintaining the error performance of SPA. Three fully-parallel LDPC decoder designs based on PG structure, PG(2,GF( 2s )) of LDPC codes are introduced. These designs differ in their bit-node (BN) and check-node (CN) architectures. Fixed-point, 9-bit quantization scheme is used to achieve better error performance. Another significant contribution of this work is the pipelining of the proposed decoder architectures to further enhance the overall throughput. These parallel and pipelined designs are implemented for 73-bit (rate 0.616) and 1057-bit (rate 0.769) regular-structured PG-LDPC codes, on Xilinx Virtex-6 LX760 FPGA and on 0.18 μm CMOS technology for ASIC. Synthesis and simulation results have shown the better performance, throughput and effectiveness of the proposed designs.

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