An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs

2015 ◽  
Vol E98.A (12) ◽  
pp. 2600-2606
Author(s):  
Yuzuru SHIZUKU ◽  
Tetsuya HIROSE ◽  
Nobutaka KUROKI ◽  
Masahiro NUMA ◽  
Mitsuji OKADA
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Flip Flop ◽  
Ultra Low Power

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

2021 ◽  
Author(s):  
Yugal Maheshwari ◽  
Kleber Stangherlin ◽  
Derek Wright ◽  
Manoj Sachdev
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Low Energy ◽  
Flip Flop ◽  
Ultra Low Power

scholarly journals Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

2019 ◽  
Vol 54 (2) ◽  
pp. 550-559 ◽  
Author(s):  
Yunpeng Cai ◽  
Anand Savanth ◽  
Pranay Prabhat ◽  
James Myers ◽  
Alex S. Weddell ◽  
...  
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Flip Flop ◽  
Ultra Low Power

Ultra-low power subthreshold flip-flop design

2009 ◽  
Author(s):  
Sagi Fisher ◽  
Adam Teman ◽  
Dmitry Vaysman ◽  
Alexander Gertsman ◽  
Orly Yadid-Pecht ◽  
...  
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Ultra Low Power

Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

2019 ◽  
Vol 18 ◽  
pp. 756-761
Author(s):  
Ahmad Karimi ◽  
Abdalhossein Rezai ◽  
Mohammad Mahdi Hajhashemkhani
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Power Pulse

scholarly journals A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Future Generation ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

2014 ◽  
Vol 61 (6) ◽  
pp. 1755-1765 ◽  
Author(s):  
Djaafar Chabi ◽  
Weisheng Zhao ◽  
Erya Deng ◽  
Yue Zhang ◽  
Nesrine Ben Romdhane ◽  
...  
Keyword(s):  
Low Power ◽  
Power Gating ◽  
Flip Flop ◽  
Ultra Low Power
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