Low-power parallel tree architecture for full search block-matching motion estimation

2004 ◽  
Author(s):  
Siou-Shen Lin ◽  
Po-Chih Tseng ◽  
Liang-Gee Chen
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Block Matching ◽  
Tree Architecture ◽  
Full Search

LOW POWER FULL SEARCH BLOCK MATCHING MOTION ESTIMATION VLSI ARCHITECTURES

2004 ◽  
Vol 13 (06) ◽  
pp. 1271-1288 ◽  
Author(s):  
MOHAMED A. ELGAMEL ◽  
MAGDY A. BAYOUMI ◽  
AHMED M. SHAMS ◽  
BERTRAND ZAVIDOVIQUE
Keyword(s):  
Power Consumption ◽  
Motion Estimation ◽  
Low Power ◽  
Block Matching ◽  
Huge Amount ◽  
Analytical Analysis ◽  
Vlsi Architectures ◽  
Simulation Results ◽  
Full Search ◽  
Low Power Architectures

Power consumption is very critical for portable video applications. During compression, the motion estimation unit consumes the largest portion of power since it performs a huge amount of computation. Different low power architectures for implementing the full-search block-matching (FSBM) motion estimation are discussed. Also, architectural enhancements to further reduce the power consumed during FSBM motion estimation without sacrificing throughput or optimality are presented. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary computations. A comparison between the different architectures including our enhancements and others is presented using simulation and analytical analysis. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancements.

LOW-POWER 2D MOTION ESTIMATION ARCHITECTURE WITH COMPLEMENTARY EMBEDDED MEMORY BANKS

2000 ◽  
Vol 10 (05n06) ◽  
pp. 229-237
Author(s):  
KYUNG-SAENG KIM ◽  
KWYRO LEE
Keyword(s):  
Motion Estimation ◽  
Data Transfer ◽  
Power Saving ◽  
Block Matching ◽  
Embedded Memory ◽  
Data Transfer Rate ◽  
Matching Algorithm ◽  
Block Matching Algorithm ◽  
Data Reading ◽  
Full Search

This letter describes a motion estimation architecture with complementary access types of memory banks, one for column vector access and the other for row vector access. It handles 2D image very efficiently for full-search block matching algorithm and maximizes a useful data transfer rate by reducing the overhead clocks for extra data reading and alignment. The results show that power saving is improved by using complementary access types of memory banks and amounts to 27.3% when the full-search block matching algorithm is applied for the CCIR-601 format compared to an identical design without the proposed enhancements.

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