A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 μm CMOS technology

2002 ◽  
Author(s):  
C.J.B. Fayomi ◽  
G.W. Roberts ◽  
M. Sawan
Keyword(s):  
Successive Approximation ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Rail To Rail

scholarly journals Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology

2021 ◽  
Vol 9 (VII) ◽  
pp. 3073-3080
Author(s):  
Sarita Chauhan
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Cmos Technology ◽  
High Energy ◽  
Sar Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Adc ◽  
Analog Cmos

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

2007 ◽  
Vol 16 (01) ◽  
pp. 1-14
Author(s):  
TASKIN KOCAK ◽  
GEORGE R. HARRIS ◽  
RONALD F. DEMARA
Keyword(s):  
Successive Approximation ◽  
Cmos Technology ◽  
Digital Systems ◽  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog Signals ◽  
Analog To Digital Conversion ◽  
Null Convention Logic ◽  
The One

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

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