Design of a low voltage charge pump circuit for RFID tag

2012 ◽  
Author(s):  
Kang Cheng Wei ◽  
M. B. I. Reaz ◽  
Md. Syedul Amin ◽  
Jubayer Jalil ◽  
Labonnah F. Rahman
Keyword(s):  
Low Voltage ◽  
Charge Pump ◽  
Rfid Tag ◽  
Charge Pump Circuit

Low Voltage Charge Pump Circuit with Double Boost Technique

2020 ◽  
Vol 140 (1) ◽  
pp. 16-23
Author(s):  
Allex Uemi ◽  
Shota Hino ◽  
Yoshihiro Masui
Keyword(s):  
Low Voltage ◽  
Charge Pump ◽  
Charge Pump Circuit

A novel low voltage and high speed CMOS charge pump circuit

2010 ◽  
Author(s):  
Fan Qiang ◽  
Fu Xiansong ◽  
Niu Pingjuan ◽  
Yang Guanghua ◽  
Gao Tiecheng
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Charge Pump ◽  
Charge Pump Circuit

scholarly journals A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1769 ◽  
Author(s):  
Choongkeun Lee ◽  
Taegun Yim ◽  
Hongil Yoon
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Clock Generator ◽  
Area Overhead ◽  
Pumping Efficiency ◽  
Charge Pump Circuit ◽  
Low Supply Voltage

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

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