Proceedings of 1994 IEEE Symposium on VLSI Circuits
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Published By IEEE

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Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586241 ◽

2005 ◽

Cited By ~ 1

Author(s):

T. Akioka ◽

S. Yukutake ◽

K. Fukui ◽

K. Mitsumoto ◽

A. Hiraishi ◽

...

Keyword(s):

Circuit Techniques

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An Experimental Cascade Cell Dynamic Memory

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586230 ◽

2005 ◽

Author(s):

D. Stark ◽

H. Watanabe ◽

T. Furuyama

Keyword(s):

Dynamic Memory

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A 256m Dram With Simplified Register Control For Low Power Self Refresh And Rapid Burn-in

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586228 ◽

2005 ◽

Author(s):

Seung-Moon Yoo ◽

Jin Man Han ◽

Ejaz Haq ◽

Sei Seung Yoon ◽

Se-Jin Jeong ◽

...

Keyword(s):

Low Power

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Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586198 ◽

2005 ◽

Cited By ~ 2

Author(s):

R.J. Landers ◽

S.S. Mahant-Shetti

Keyword(s):

Low Power ◽

High Density ◽

Gate Arrays

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A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586217 ◽

2005 ◽

Cited By ~ 3

Author(s):

T. Tanzawa ◽

Y. Tanaka ◽

T. Tanaka ◽

H. Nakamura ◽

H. Oodaira ◽

...

Keyword(s):

Low Voltage ◽

Charge Pump ◽

High Density ◽

Flash Memories ◽

Charge Pump Circuit

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A Fully Monolithic 1.25ghz cmos Frequency Synthesizer

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586249 ◽

2005 ◽

Cited By ~ 9

Author(s):

M. Soyuer ◽

J.F. Ewen ◽

H.L. Chuang

Keyword(s):

Frequency Synthesizer

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A Dynamic Current-offset Calibration (dcc) Sense Amplifier With Fish-bone Shaped Bitline (fbb) For High-density Srams

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586243 ◽

2005 ◽

Cited By ~ 1

Author(s):

J. Takahashi ◽

T. Wada ◽

Y. Nishimura

Keyword(s):

Fish Bone ◽

High Density ◽

Sense Amplifier

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A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586240 ◽

2005 ◽

Cited By ~ 6

Author(s):

H. Nambu ◽

K. Kanetani ◽

Y. Idei ◽

T. Masuda ◽

K. Higeta ◽

...

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A 1.5v Video-Speed Current-Mode Current-Tree A/d Converter

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586169 ◽

2005 ◽

Cited By ~ 2

Author(s):

H. Hasegawa ◽

M. Yotsuyanagi ◽

M. Yamaguchi ◽

K. Sone

Keyword(s):

Current Mode

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Folded-read And Open/folded-restore Bit-line Scheme For Giga Scale 6f2 Dram Cell

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586246 ◽

2005 ◽

Author(s):

D. Takashima ◽

H. Nakano ◽

T. Ozaki ◽

Y. Oowaki ◽

S. Shiratake ◽

...

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Proceedings of 1994 IEEE Symposium on VLSI CircuitsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v

An Experimental Cascade Cell Dynamic Memory

A 256m Dram With Simplified Register Control For Low Power Self Refresh And Rapid Burn-in

Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays

A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories

A Fully Monolithic 1.25ghz cmos Frequency Synthesizer

A Dynamic Current-offset Calibration (dcc) Sense Amplifier With Fish-bone Shaped Bitline (fbb) For High-density Srams

A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram

A 1.5v Video-Speed Current-Mode Current-Tree A/d Converter

Folded-read And Open/folded-restore Bit-line Scheme For Giga Scale 6f2 Dram Cell

Proceedings of 1994 IEEE Symposium on VLSI Circuits
Latest Publications