A high speed low power CMOS clock driver using charge recycling technique

2002 ◽  
Author(s):  
I. Bouras ◽  
Y. Liaperdos ◽  
A. Arapoyanni
Keyword(s):  
Low Power ◽  
High Speed ◽  
Charge Recycling ◽  
Low Power Cmos ◽  
Recycling Technique

A CHARGE RECYCLING TECHNIQUE FOR THE DESIGN OF LOW POWER CMOS CLOCK DRIVERS

1999 ◽  
Vol 09 (03n04) ◽  
pp. 169-180
Author(s):  
S. NIKOLAIDIS ◽  
E. D. KYRIAKIS-BITZAROS
Keyword(s):  
Low Power ◽  
Total Power ◽  
Design Parameters ◽  
Clock Signal ◽  
Silicon Area ◽  
Control Overhead ◽  
Charge Recycling ◽  
Low Power Cmos ◽  
A Charge ◽  
Recycling Technique

The design of low power CMOS clock drivers using a charge recycling technique is introduced in this paper. Considering a clock signal and its complement, the half of the charge stored in the load capacitances is reused in every clock edge. The proposed circuit exploits the inherent input-output delay of the driver for the generation of all necessary control signals, using fully digital logic and conventional technology. Extensive simulations of the circuit have been performed and the influence of various design parameters on its response has been studied. Compared to traditional taper buffers, power savings over 45% are obtained for the output load transitions whereas the total power reduction decreases by 10% to 35% due to control overhead. Moreover, no speed degradation is observed but almost a duplication of the silicon area is required.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

Analysis and design of high-speed and low-power CMOS PLAs

2001 ◽  
Vol 36 (8) ◽  
pp. 1250-1262 ◽  
Author(s):  
Jinn-Shyan Wang ◽  
Ching-Rong Chang ◽  
Chingwei Yeh
Keyword(s):  
Low Power ◽  
High Speed ◽  
Analysis And Design ◽  
Low Power Cmos

An ultra high speed low-power CMOS integrated current comparator

2008 ◽  
Author(s):  
Soheil Ziabakhsh ◽  
Hosein Alavi Rad ◽  
Alireza Saberkari ◽  
Shahriar Baradaran Shokouhi
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Comparator ◽  
Ultra High Speed ◽  
Low Power Cmos

1.5 V high speed low power CMOS current sense amplifier

1995 ◽  
Vol 31 (23) ◽  
pp. 1991-1993 ◽  
Author(s):  
Y.K. Seng ◽  
S.S. Rofail
Keyword(s):  
Low Power ◽  
High Speed ◽  
Sense Amplifier ◽  
Low Power Cmos
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