High-speed high-precision voltage-mode MIN/MAX circuits in CMOS technology

2002 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramirez-Angula ◽  
J. Tombs
Keyword(s):  
High Precision ◽  
High Speed ◽  
Cmos Technology ◽  
Voltage Mode ◽  
Precision Voltage

HIGH SPEED HIGH PRECISION VOLTAGE-MODE MAX AND MIN CIRCUITS

2007 ◽  
Vol 16 (02) ◽  
pp. 233-244 ◽  
Author(s):  
SARANG KAZEMI NIA ◽  
ABDOLLAH KHOEI ◽  
KHEIROLLAH HADIDI
Keyword(s):  
High Precision ◽  
High Speed ◽  
Voltage Mode ◽  
Precision Voltage ◽  
Simple Expansion ◽  
Differential Pair ◽  
Simulation Results ◽  
Hspice Simulation

This paper presents a new high speed voltage-mode MAX–MIN method for fuzzy applications. In the proposed circuits, a differential pair is employed to choose the desired input. In addition to high speed, high precision and simple expansion for multiple inputs are the main advantages of this method. HSPICE simulation results show that the proposed circuit has maximum of 1% error at 100 MHz.

High-speed high-precision min/max circuits in CMOS technology

2000 ◽  
Vol 36 (8) ◽  
pp. 697 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramírez-Angulo ◽  
J. Martínez-Heredia
Keyword(s):  
High Precision ◽  
High Speed ◽  
Cmos Technology

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Variable step control to improve scanning speed of gene sequencing stage

2021 ◽  
pp. 002029402110022
Author(s):  
Xiaohua Zhou ◽  
Jianbin Zheng ◽  
Xiaoming Wang ◽  
Wenda Niu ◽  
Tongjian Guo
Keyword(s):  
Motion Control ◽  
High Precision ◽  
High Speed ◽  
Stable State ◽  
Gene Sequencing ◽  
Scanning Speed ◽  
Settling Time ◽  
Step Motion ◽  
Variable Step ◽  
Step Control

High-speed scanning is a huge challenge to the motion control of step-scanning gene sequencing stage. The stage should achieve high-precision position stability with minimal settling time for each step. The existing step-scanning scheme usually bases on fixed-step motion control, which has limited means to reduce the time cost of approaching the desired position and keeping high-precision position stability. In this work, we focus on shortening the settling time of stepping motion and propose a novel variable step control method to increase the scanning speed of gene sequencing stage. Specifically, the variable step control stabilizes the stage at any position in a steady-state interval rather than the desired position on each step, so that reduces the settling time. The resulting step-length error is compensated in the next acceleration and deceleration process of stepping to avoid the accumulation of errors. We explicitly described the working process of the step-scanning gene sequencer and designed the PID control structure used in the variable step control for the gene sequencing stage. The simulation was performed to check the performance and stability of the variable step control. Under the conditions of the variable step control where the IMA6000 gene sequencer prototype was evaluated extensively. The experimental results show that the real gene sequencer can step 1.54 mm in 50 ms period, and maintain a high-precision stable state less than 30 nm standard deviation in the following 10 ms period. The proposed method performs well on the gene sequencing stage.

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