High-speed high-precision min/max circuits in CMOS technology

2000 ◽  
Vol 36 (8) ◽  
pp. 697 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramírez-Angulo ◽  
J. Martínez-Heredia
Keyword(s):  
High Precision ◽  
High Speed ◽  
Cmos Technology

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Variable step control to improve scanning speed of gene sequencing stage

2021 ◽  
pp. 002029402110022
Author(s):  
Xiaohua Zhou ◽  
Jianbin Zheng ◽  
Xiaoming Wang ◽  
Wenda Niu ◽  
Tongjian Guo
Keyword(s):  
Motion Control ◽  
High Precision ◽  
High Speed ◽  
Stable State ◽  
Gene Sequencing ◽  
Scanning Speed ◽  
Settling Time ◽  
Step Motion ◽  
Variable Step ◽  
Step Control

High-speed scanning is a huge challenge to the motion control of step-scanning gene sequencing stage. The stage should achieve high-precision position stability with minimal settling time for each step. The existing step-scanning scheme usually bases on fixed-step motion control, which has limited means to reduce the time cost of approaching the desired position and keeping high-precision position stability. In this work, we focus on shortening the settling time of stepping motion and propose a novel variable step control method to increase the scanning speed of gene sequencing stage. Specifically, the variable step control stabilizes the stage at any position in a steady-state interval rather than the desired position on each step, so that reduces the settling time. The resulting step-length error is compensated in the next acceleration and deceleration process of stepping to avoid the accumulation of errors. We explicitly described the working process of the step-scanning gene sequencer and designed the PID control structure used in the variable step control for the gene sequencing stage. The simulation was performed to check the performance and stability of the variable step control. Under the conditions of the variable step control where the IMA6000 gene sequencer prototype was evaluated extensively. The experimental results show that the real gene sequencer can step 1.54 mm in 50 ms period, and maintain a high-precision stable state less than 30 nm standard deviation in the following 10 ms period. The proposed method performs well on the gene sequencing stage.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

High-speed and high-precision fluorescence-based cell count and viability assays using the Cellaca™ MX high-throughput cell counter

Cytotherapy ◽  
2021 ◽  
Vol 23 (5) ◽  
pp. S97
Author(s):  
J. Bell ◽  
Y. Huang ◽  
S. Yung ◽  
H. Qazi ◽  
C. Hernandez ◽  
...  
Keyword(s):  
Cell Count ◽  
High Precision ◽  
High Throughput ◽  
High Speed ◽  
Cell Counter
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