The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

2003 ◽  
Author(s):  
M.S. Hrishikesh ◽  
N.P. Jouppi ◽  
K.I. Farkas ◽  
D. Burger ◽  
S.W. Keckler ◽  
...  
Keyword(s):  
Pipeline Stage

Optimal pipeline stage balancing in the presence of large isolated interconnect delay

2017 ◽  
Vol 53 (4) ◽  
pp. 229-231 ◽  
Author(s):  
M. Olivieri ◽  
F. Menichelli ◽  
A. Mastrandrea
Keyword(s):  
Pipeline Stage ◽  
Interconnect Delay

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

2002 ◽  
Vol 30 (2) ◽  
pp. 14-24 ◽  
Author(s):  
M. S. Hrishikesh ◽  
Doug Burger ◽  
Norman P. Jouppi ◽  
Stephen W. Keckler ◽  
Keith I. Farkas ◽  
...  
Keyword(s):  
Pipeline Stage
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