Optimal pipeline stage balancing in the presence of large isolated interconnect delay

2017 ◽  
Vol 53 (4) ◽  
pp. 229-231 ◽  
Author(s):  
M. Olivieri ◽  
F. Menichelli ◽  
A. Mastrandrea
Keyword(s):  
Pipeline Stage ◽  
Interconnect Delay

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Air-Gap Technology With a Large Void-Fraction for Global Interconnect Delay Reduction

2021 ◽  
pp. 1-7
Author(s):  
Clarissa Prawoto ◽  
Zichao Ma ◽  
Ying Xiao ◽  
Salahuddin Raju ◽  
Mansun Chan
Keyword(s):  
Void Fraction ◽  
Air Gap ◽  
Delay Reduction ◽  
Large Void ◽  
Interconnect Delay ◽  
Global Interconnect ◽  
Gap Technology

Sol–gel deposited xerogel, aerogel and porogen based porous low-k thin films: A comparative investigation

2021 ◽  
pp. 2140019
Author(s):  
Swati Gupta ◽  
Anil Gaikwad ◽  
Ashok Mahajan ◽  
Lin Hongxiao ◽  
He Zhewei
Keyword(s):  
Dielectric Constant ◽  
Sol Gel ◽  
Comparative Investigation ◽  
Crosstalk Noise ◽  
Nanoelectronic Devices ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Xerogel Films ◽  
Low K ◽  
Porosity Percentage

Low dielectric constant (Low-[Formula: see text]) films are used as inter layer dielectric (ILD) in nanoelectronic devices to reduce interconnect delay, crosstalk noise and power consumption. Tailoring capability of porous low-[Formula: see text] films attracted more attention. Present work investigates comparative study of xerogel, aerogel and porogen based porous low-[Formula: see text] films. Deposition of SiO2 and incorporation of less polar bonds in film matrix is confirmed using Fourier Transform Infra-Red Spectroscopy (FTIR). Refractive indices (RI) of xerogel, aerogel and porogen based low-[Formula: see text] films observed to be as low as 1.25, 1.19 and 1.14, respectively. Higher porosity percentage of 69.46% is observed for porogen-based films while for shrinked xerogel films, it is lowered to 45.47%. Porous structure of low-[Formula: see text] films has been validated by using Field Emission Scanning Electron Microscopy (FE-SEM). The pore diameters of porogen based annealed samples were in the range of 3.53–25.50 nm. The dielectric constant ([Formula: see text]) obtained from RI for xerogel, aerogel and porogen based films are 2.58, 2.20 and 1.88, respectively.

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