Biased-humidity testing is a critical reliability qualification requirement for integrated circuit packages. The benchmark of THB (Temperature Humidity Bias) at 85C/85%RH/bias for 1000 hours is a long duration test, so biased-HAST (biased Highly Accelerated Stress Test) conditions are adopted. Accelerated biased-HAST durations are based on aluminum corrosion failure mechanisms and may not be applicable to other materials such as in flip-chip packages. One such failure mechanism is discussed here.
Flip-chip packages with build-up substrates were exposed to biased-humidity at 85C, 110C, or 130C and 85%RH. After 96 hours of 130C/85%RH/bias, failures occurred with signatures ranging from bake-recoverable leakage to shorts. Physical failure analysis revealed copper migration in the substrate build-up dielectric rather than classical CAF (Conductive Anodic Filament) within the substrate core. No copper migration occurred with conditions of 110C/85%RH/bias, 85C/85%RH/bias, or 130C/85%RH/no-bias. Given that the JEDEC biased humidity durations are 96 hours at 130C/85%RH, 264 hours at 110C/85%RH, or 1000 hours at 85C/85%RH, it is concluded that the JEDEC acceleration function is not applicable for this failure mechanism.
A failure model is proposed based on humidity induced reduction of the glass transition temperature (Tg) of the build-up dielectric. Bond strength decreases and free volume increases above Tg, and the combination results in the formation of localized channels in the build-up dielectric where electrochemical migration of copper occurs under bias and humidity. Copper migration does not occur for conditions of humidity/bias below Tg, humidity/no-bias above Tg, and no humidity/bias near Tg. This indicates there is likely a threshold in humidity and/or temperature, below which copper migration does not occur. These results further demonstrate that caution must be used when employing accelerated reliability tests, as they may introduce failure mechanisms that would not occur in the field.