InGaAs metal-oxide-semiconductor FETs with self-aligned Ni-Alloy source/drain

2015 ◽  
Author(s):  
Shin-Yuan Wang ◽  
Chao-Hsin Chien ◽  
Jin-Ju Lin ◽  
Chun-Yen Chang
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ni Alloy

Fermi level tuning using the Hf-Ni alloy system as a gate electrode in metal-oxide-semiconductor devices

2012 ◽  
Vol 112 (1) ◽  
pp. 013717 ◽  
Author(s):  
Jonathan Avner Rothschild ◽  
Aya Cohen ◽  
Anna Brusilovsky ◽  
Lior Kornblum ◽  
Yaron Kauffmann ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Fermi Level ◽  
Semiconductor Devices ◽  
Alloy System ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Electrode ◽  
Ni Alloy

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Optimized Al-doped TiO2 gate insulator for metal-oxide-semiconductor capacitor on Ge substrate

2021 ◽  
Author(s):  
Dong Gun Kim ◽  
Cheol Hyun An ◽  
Sanghyeon Kim ◽  
Dae Seon Kwon ◽  
Junil Lim ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Leakage Current ◽  
Tio2 Film ◽  
Single Layer ◽  
Atomic Layer ◽  
Metal Oxide Semiconductor ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
High K ◽  
Metal Oxide Semiconductor Capacitor

Atomic layer deposited TiO2- and Al2O3-based high-k gate insulator (GI) were examined for the Ge-based metal-oxide-semiconductor capacitor application. The single-layer TiO2 film showed a too high leakage current to be...

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