A New Approach for Transient Fault Injection Using Symbolic Simulation

2008 ◽  
Author(s):  
Ashish Darbari ◽  
Bashir Al Hashimi ◽  
Peter Harrod ◽  
Daryl Bradley
Keyword(s):  
Fault Injection ◽  
Symbolic Simulation ◽  
Transient Fault ◽  
New Approach

scholarly journals Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

Electronics ◽  
2018 ◽  
Vol 8 (1) ◽  
pp. 24 ◽  
Author(s):  
Maria Muñoz-Quijada ◽  
Samuel Sanchez-Barea ◽  
Daniel Vela-Calderon ◽  
Hipolito Guzman-Miranda
Keyword(s):  
Radiation Effects ◽  
Digital Circuits ◽  
Fault Injection ◽  
Description Language ◽  
New Approach ◽  
Internal Memory ◽  
Fine Grain ◽  
Radiation Induced ◽  
Hardware Description ◽  
Modular Redundancy

Radiation effects can induce, amongst other phenomena, logic errors in digital circuits and systems. These logic errors corrupt the states of the internal memory elements of the circuits and can propagate to the primary outputs, affecting other onboard systems. In order to avoid this, Triple Modular Redundancy is typically used when full robustness against these phenomena is needed. When full triplication of the complete design is not required, selective hardening can be applied to the elements in which a radiation-induced upset is more likely to propagate to the main outputs of the circuit. The present paper describes a new approach for selectively hardening digital electronic circuits by design, which can be applied to digital designs described in the VHDL Hardware Description Language. When the designer changes the datatype of a signal or port to a hardened type, the necessary redundancy is automatically inserted. The automatically hardening features have been compiled into a VHDL package, and have been validated both in simulation and by means of fault injection.

scholarly journals TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform

2021 ◽  
Vol 11 (3) ◽  
pp. 2704
Author(s):  
Sharath Kumar Y. N. ◽  
Dinesha P.
Keyword(s):  
Integrated Circuits ◽  
Digital Circuits ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Asynchronous Circuits ◽  
Fault Coverage ◽  
Asynchronous Circuit ◽  
Hardware Complexity ◽  
Transient Fault ◽  
Fault Tolerant System

Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.

scholarly journals An arithmetic approach to the analysis of multiple faults verification and synthesis at switch-level

2021 ◽  
Author(s):  
Mohammad Reza Samadpour Javaheri
Keyword(s):  
Fault Injection ◽  
Signal Propagation ◽  
Cmos Technology ◽  
Cmos Circuits ◽  
Charge Sharing ◽  
New Approach ◽  
Multiple Faults ◽  
Circuit Verification ◽  
Level Model ◽  
Multi Level

Switch-level modeling and simulation has become an important method of predicting the behaviour of CMOS circuits under the presence of faults. Many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength can be reliably modeled using this technique. This paper presents an algorithm for modeling directional and bi-directional CMOS circuits with an arithmetic solution for circuit verification and fault synthesis. This new approach is capable of simulating multiple fault injection into the circuit and speeds up switch-level simulation. Other advantages of this algorithm are its application in the mapping of single and multiple faults from switch level to gate level and the ability to function as a multi-level model. Multiple faults can be of the same or different types. Experimental results using Cadence tools show that the algorithm is successful and reliable for CMOS technology.

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