Delay and power consumption of fault tolerant data busses in VDSM technology

INTERACT-2010 ◽  
2010 ◽  
Author(s):  
A. Sathish ◽  
M. Chennakesavulu ◽  
M. Madhavi Latha ◽  
K. Lal Kishore
Keyword(s):  
Power Consumption ◽  
Fault Tolerant

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

2020 ◽  
pp. 2120003
Author(s):  
Zhengfeng Huang ◽  
Zian Su ◽  
Tianming Ni ◽  
Qi Xu ◽  
Haochen Qi ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Fault Tolerant ◽  
Cross Layer ◽  
Charge Sharing ◽  
Single Node ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Modular Redundancy ◽  
Voltage Swing

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant Arithmetic

2019 ◽  
Vol 28 (14) ◽  
pp. 1950244
Author(s):  
Ahmad Towhidy ◽  
Reza Omidi ◽  
Karim Mohammadi
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Design Procedure ◽  
Current Mode ◽  
Vlsi Circuits ◽  
Technology Scaling ◽  
Residue Code ◽  
Logic Unit

Due to technology scaling, reliability has become one of the biggest challenges in VLSI circuits. A number of techniques have been introduced in the literature, especially for arithmetic and logic unit in computers. One of well-known schemes for fault-tolerant arithmetic is the use of arithmetic residue codes. A key problem with most of the previous works regarding residue-based checker is that these methods impose an unacceptable area penalty. In this paper, we propose a novel residue checker with current mode multi-valued logic (CMMVL). A plain design procedure with arbitrary modulo is introduced; also a more efficient integrated scheme for modulo 3 has been demonstrated. The results of the plain CMMVL scheme showed up to 19.5% and 42.9% lower delay and power consumption, respectively, compared with those of the conventional CMOS. Also, utilizing the integrated CMMVL provided, on average, about 17.7% and 80.2% lower delay and power consumption, respectively.

Low power modular redundancy: a power efficient fault tolerant approach for digital circuits

2016 ◽  
Vol 35 (3) ◽  
Author(s):  
M. Saeed Ansari ◽  
Ali Mahani ◽  
Karim Mohammadi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Design Methodology ◽  
Digital Circuits ◽  
Fault Tolerant ◽  
Sleep Mode ◽  
Clock Generator ◽  
The Third ◽  
Triple Modular Redundancy ◽  
Modular Redundancy

Purpose To increase protection level against transient faults, circuit designers usually take advantage of redundant structures like Triple Modular Redundancy (TMR). Since redundancy compel a significant power overhead, proposing a low power fault tolerant technique in digital circuits is the main objective of this research work. Design/methodology/approach In order to moderate power consumption, we use a dual to triple modular redundancy. In fact, we put one of the modules in a TMR system in sleep mode while the other two operating modules are producing the same outputs. Once a mismatch is detected, the third one exits the sleep mode and the dual modular redundancy (DMR) approach turns into a conventional TMR. Also a novel stoppable clock generator is proposed to handle the sleep mode of the third module. Finally, a new three-input majority voter, compatible with our proposed technique, is presented. Findings Power analysis of combinational circuit benchmarks, ISCAS85, and ISCAS89 as sequential circuit benchmarks are depicted. Simulation results show the power reduction of up to 30% in comparison with the conventional modular redundancy approach. Originality/value Since modular redundancy is the most effective and the most well-known fault tolerant approach which is widely used in reliable circuits designs, it is important to reduce its power consumption. In this paper configuring the sleep mode operation of a circuit and stoppable clock generator lead to a new TMR technique in which the power consumption is strongly reduced.

Power Consumption of Fault Tolerant Busses

2008 ◽  
Vol 16 (5) ◽  
pp. 542-553 ◽  
Author(s):  
D. Rossi ◽  
A.K. Nieuwland ◽  
S.V.E. van Dijk ◽  
R.P. Kleihorst ◽  
C. Metra
Keyword(s):  
Power Consumption ◽  
Fault Tolerant

Power consumption of fault tolerant codes: the active elements

2004 ◽  
Author(s):  
D. Rossi ◽  
V.E.S. van Dijk ◽  
R.P. Kleihorst ◽  
A.K. Nieuwland ◽  
C. Metra
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Active Elements

scholarly journals Fault-tolerant architecture for Cache : Summaries, Assessments and Trends

2021 ◽  
Vol 2113 (1) ◽  
pp. 012068
Author(s):  
Xuru Wang ◽  
Xin Gao ◽  
Zongnan Liang ◽  
Jiawei Nian ◽  
Hongjin Liu
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Future Development ◽  
Fault Tolerant ◽  
Development Trend ◽  
The Other ◽  
Architecture Design ◽  
Related Research ◽  
Cache Architecture ◽  
The Future

Abstract Fault-tolerant design of cache is a key aspect of highly reliable processor design. In this paper, based on the key metrics in Cache architecture design: reliability, power consumption, latency and area, we divided the related research into two categories: one is to maximize reliability with guaranteed latency, power consumption and area, the other is to minimize latency, power consumption and area loss while ensuring fault tolerance reliability. Based on the classification, by analyzing different studies of Data and Tag in Cache, this paper gives the characteristics of these methods and the future development trend.

scholarly journals POWER-CONSUMPTION-ORIENTED CHECKABILITY FOR FPGA-BASED COMPONENTS OF SAFETY-RELATED SYSTEMS

2019 ◽  
pp. 118-126
Author(s):  
Oleksandr Drozd ◽  
Viktor Antoniuk ◽  
Miroslav Drozd ◽  
Volodymyr Karpinskyi ◽  
Pavlo Bykovyy
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Logical Form ◽  
Control Object ◽  
Fpga Implementation ◽  
Dual Mode ◽  
Increased Risk ◽  
Input Signals ◽  
Analytical Assessment ◽  
The Common

This paper is dedicated to the problem of the circuit checkability of components in the safety-related systems, which operate objects of the increased risk and are aimed at ensuring safety of both a system and a control object for accident prevention and a decrease in their consequences. Importance of the checkability of the circuits for ensuring safety in critical applications is emphasized as safety is based on the use of fault tolerant circuitry decisions and their efficiency is defined by the circuit checkability. Development of a logical checkability from testability to structurally functional and dual-mode model which formalizes a problem of the hidden faults and defines ways of its solution is shown. The limitation of a logical checkability in detection of faults in chains of the common signals and the need for development of checkability out of the limits of a logical form, including suitability to checking the circuits on the basis of their power consumption is considered. Power-consumption-oriented checkability (Power-checkability) allowing detection of faults in chains of the common signals is defined. Its analytical assessment for the circuits implemented in FPGA is offered. Experiments providing estimation of power-checkability for FPGA-implementation of iterative array multipliers with various activities of input signals are carried out.

scholarly journals Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

2011 ◽  
Vol 2011 ◽  
pp. 1-25 ◽  
Author(s):  
R. Al-Haddad ◽  
R. Oreifej ◽  
R. A. Ashraf ◽  
R. F. DeMara
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Repair Time ◽  
Self Healing ◽  
Partial Reconfiguration ◽  
Organic System ◽  
Dynamic Partial Reconfiguration ◽  
Novel Approach ◽  
Field Programmable ◽  
Sobel Edge Detection

As reconfigurable devices' capacities and the complexity of applications that use them increase, the need forself-relianceof deployed systems becomes increasingly prominent. Organic computing paradigms have been proposed for fault-tolerant systems because they promote behaviors that allow complex digital systems to adapt and survive in demanding environments. In this paper, we develop asustainable modular adaptive redundancy technique (SMART)composed of a two-layered organic system. The hardware layer is implemented on a XilinxVirtex-4Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach calledreconfigurable adaptive redundancy system (RARS). The software layer supervises the organic activities on the FPGA and extends the self-healing capabilities through application-independent, intrinsic, and evolutionary repair techniques that leverage the benefits of dynamic partial reconfiguration (PR). SMART was evaluated using a Sobel edge-detection application and was shown to tolerate stressful sequences of injected transient and permanent faults while reducing dynamic power consumption by 30% compared to conventionaltriple modular redundancy (TMR)techniques, with nominal impact on the fault-tolerance capabilities. Moreover, PR is employed to keep the system on line while under repair and also to reduce repair time. Experiments have shown a 27.48% decrease in repair time when PR is employed compared to the full bitstream configuration case.

Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection

2018 ◽  
Vol 65 (4) ◽  
pp. 1293-1302 ◽  
Author(s):  
Ricardo Gonzalez-Toral ◽  
Shanshan Liu ◽  
Pedro Reviriego ◽  
Juan Antonio Maestro
Keyword(s):  
Power Consumption ◽  
Fault Tolerant
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