scholarly journals POWER-CONSUMPTION-ORIENTED CHECKABILITY FOR FPGA-BASED COMPONENTS OF SAFETY-RELATED SYSTEMS

2019 ◽  
pp. 118-126
Author(s):  
Oleksandr Drozd ◽  
Viktor Antoniuk ◽  
Miroslav Drozd ◽  
Volodymyr Karpinskyi ◽  
Pavlo Bykovyy
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Logical Form ◽  
Control Object ◽  
Fpga Implementation ◽  
Dual Mode ◽  
Increased Risk ◽  
Input Signals ◽  
Analytical Assessment ◽  
The Common

This paper is dedicated to the problem of the circuit checkability of components in the safety-related systems, which operate objects of the increased risk and are aimed at ensuring safety of both a system and a control object for accident prevention and a decrease in their consequences. Importance of the checkability of the circuits for ensuring safety in critical applications is emphasized as safety is based on the use of fault tolerant circuitry decisions and their efficiency is defined by the circuit checkability. Development of a logical checkability from testability to structurally functional and dual-mode model which formalizes a problem of the hidden faults and defines ways of its solution is shown. The limitation of a logical checkability in detection of faults in chains of the common signals and the need for development of checkability out of the limits of a logical form, including suitability to checking the circuits on the basis of their power consumption is considered. Power-consumption-oriented checkability (Power-checkability) allowing detection of faults in chains of the common signals is defined. Its analytical assessment for the circuits implemented in FPGA is offered. Experiments providing estimation of power-checkability for FPGA-implementation of iterative array multipliers with various activities of input signals are carried out.

scholarly journals Checkability of the circuits in FPGA designs according to power dissipation

2019 ◽  
pp. 3-9
Author(s):  
V. V. Antoniuk ◽  
A. V. Drozd ◽  
J. V. Drozd ◽  
H. S. Stepova
Keyword(s):  
Power Dissipation ◽  
Input Data ◽  
Digital Circuits ◽  
Short Circuit ◽  
Logical Form ◽  
Dual Mode ◽  
Fpga Chip ◽  
Analytical Assessment ◽  
Short Circuits ◽  
Emergency Mode

The authors consider the checkability issues of FPGA designs and analyze the logical (structural and structurally functional) checkability. The paper describes the features of safety-related systems that can operate in normal and emergency mode. In these modes different input data are fed to the inputs of the digital circuits of the components, which leads to an expansion of the structurally functional checkability to dual-mode. The paper shows the problem of hidden faults, which can accumulate in the normal mode and manifest themselves in the emergency mode. The features of checkability of circuits in FPGA projects and its advantages important for critical applications are noted. The limitations of the logical checkability of the circuits are analyzed, as well as the possibility and expediency of expanding the traditionally used logical form to power usage checkability. The study defines the checkability of circuits in FPGA projects by power usage and determines its subtypes — lower and upper checkability. Lower checkability is important in identifying faults that lead to lower power usage, for example, in chains of common signals, such as reset or synchronization. The upper one is important for identifying faults that increase the level of power usage, for example, short-circuits. The authors identify the possibility of assessing the power usage checkability of FPGA projects in terms of the power dissipation or power consumption and indicate the possibility of developing upper checkability by the dissipated power. The features of power dissipation monitoring for FPGA projects are noted. An analytical assessment for the checkability of circuits for short-circuit faults, which increase the dissipated power, and the organization of monitoring its excess are proposed. Experiments in Quartus Prime Lite CAD to assess upper checkability by power dissipation of scalable shift register circuits, that are implemented in FPGA projects, based on default IP-Core and a custom VHDL description, are carried out. The paper presents experimental results, that estimate the dependence of the checkability level on the area, occupied by the circuit on the FPGA chip.

An analytical model for the power consumption of Dual‐Mode EEE

2016 ◽  
Vol 52 (15) ◽  
pp. 1308-1310 ◽  
Author(s):  
M. Mostowfi ◽  
K. Shafie
Keyword(s):  
Power Consumption ◽  
Analytical Model ◽  
Dual Mode

The risk of aspiration in Dettol poisoning: a retrospective cohort study

1995 ◽  
Vol 14 (2) ◽  
pp. 190-191 ◽  
Author(s):  
Thomas Y.K. Chan ◽  
Julian A.J.H. Critchley ◽  
Joseph T.F. Lau
Keyword(s):  
Retrospective Cohort ◽  
Matched Control ◽  
Gastric Lavage ◽  
Common Occurrence ◽  
Pine Oil ◽  
Control Subjects ◽  
Increased Risk ◽  
The Common ◽  
Risk Of Aspiration ◽  
Increase In Risk

1 To determine if the risk of aspiration is increased in 'Dettol' (4.8% chloroxylenol, pine oil and isopropyl alco hol) poisoning and the factors that may be responsible, a study was made of 89 patients and 89 matched control subjects with other forms of poisoning admitted to the Prince of Wales Hospital, Hong Kong. 2 Aspiration was more common in patients with Dettol poisoning (8% vs 3%, P = 0.16). There were more control subjects with drowsiness at presentation (54% vs 24%, P < 0.0001), but the use of gastric lavage (88% vs 64%, P < 0.001) and the occurrence of vomiting (62% vs 17%, P < 0.0001) were more common in patients with Dettol poisoning. 3 Our findings suggest that Dettol poisoning may be asso ciated with an increased risk of aspiration. This increase in risk may be related to the use of gastric lavage and the common occurrence of vomiting in patients with Dettol poisoning.

scholarly journals Are complications of endoscopic sphincterotomy age related?

Gut ◽  
1997 ◽  
Vol 41 (4) ◽  
pp. 545-548 ◽  
Author(s):  
G T Deans ◽  
P Sedman ◽  
D F Martin ◽  
C M S Royston ◽  
C K Leow ◽  
...  
Keyword(s):  
Laparoscopic Cholecystectomy ◽  
Endoscopic Sphincterotomy ◽  
Short Term ◽  
Endoscopic Retrograde ◽  
Younger Patients ◽  
Age Related ◽  
Increased Risk ◽  
Ascending Cholangitis ◽  
Retroperitoneal Perforation ◽  
The Common

Background—Endoscopic retrograde cholangiopancreatography sphincterotomy is increasingly performed in younger patients undergoing laparoscopic cholecystectomy. However, the safety of endo- scopic sphincterotomy in this age group, relative to that in older patients, is unknown.Aim—To determine whether the development of short term complications following endoscopic sphincterotomy is age related.Patients and methods—A prospective multicentre audit of 958 patients (mean age 73, range 14–97, years) undergoing a total of 1000 endoscopic sphincterotomies.Results—Two deaths occurred, both from postsphincterotomy acute pancreatitis. Postprocedural complications developed in 24 patients: pancreatitis in 10, ascending cholangitis in seven, bleeding in four, and retroperitoneal perforation in three. There were six complications (five cases of pancreatitis and one bleed; 2.2%) and no deaths in the 281 (29.3%) patients aged under 65 years. In comparison, 18 (2.6%) of the 677 patients aged over 65 years developed a complication (cholangitis in seven, pancreatitis in five, bleeding in three, and perforation in three). Patients under 35, 45, 55, and 65 years were not at significantly increased risk of complication than those over these ages (relative risk for those under compared with those over 65 years 0.83, 95% confidence intervals 0.41–1.67, p=0.74).Conclusion—Short term complications following endoscopic sphincterotomy are not related to age. Younger patients undergoing laparoscopic cholecystectomy need not be denied endoscopic sphincterotomy for fear that the risks are greater than if they undergo surgical exploration of the common bile duct.

Excess mortality of mental disorder

1998 ◽  
Vol 173 (1) ◽  
pp. 11-53 ◽  
Author(s):  
Clare Harris ◽  
Brian Barraclough
Keyword(s):  
Mental Disorders ◽  
Mental Disorder ◽  
English Language ◽  
Common Mental Disorders ◽  
Premature Death ◽  
Medline Search ◽  
Risk Of Death ◽  
Increased Risk ◽  
Standardised Mortality Ratios ◽  
The Common

BackgroundWe describe the increased risk of premature death from natural and from unnatural causes for the common mental disorders.MethodWith a Medline search (1966–1995) we found 152 English language reports on the mortality of mental disorder which met our inclusion criteria. From these reports, covering 27 mental disorder categories and eight treatment categories, we calculated standardised mortality ratios (SMRs) and 95% confidence intervals (CIs) for all causes of death, all natural causes and all unnatural causes; and for most, SMRs for suicide, other violent causes and specific natural causes.ResultsHighest risks of premature death, from both natural and unnatural causes, are for substance abuse and eating disorders. Risk of death from unnatural causes is especially high for the functional disorders, particularly schizophrenia and major depression. Deaths from natural causes are markedly increased for organic mental disorders, mental retardation and epilepsy.ConclusionAll mental disorders have an increased risk of premature death.

General Method to Design Reversible Universal n-Bit Up/Down Counters

2020 ◽  
Vol 29 (10) ◽  
pp. 2050165
Author(s):  
Zeinab Kalantari ◽  
Mohammad Eshghi ◽  
Majid Mohammadi ◽  
Somayeh Jassbi
Keyword(s):  
Power Consumption ◽  
Electronic Devices ◽  
Reducing Power ◽  
Sequential Circuits ◽  
Quantum Cost ◽  
Multiple Outputs ◽  
Reversible Circuits ◽  
Direct Design ◽  
The Common ◽  
General Method

With the growing trend towards reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers, and designing reversible circuits is one of the approaches proposed for reducing power consumption. Although several studies have been done in the field of synthesizing combinational reversible circuits, little work has been done for designing reversible sequential circuits. Furthermore, many researches in this context use traditional designs which replace latches, flip-flops and associated combinational gates with their reversible counterparts. This traditional technique is not very promising, because it leads to high quantum cost (QC) and garbage outputs. Recently, researchers have proposed direct design of reversible sequential circuits using Reed Muller expressions to obtain next state output. Since most sequential circuits have multiple outputs, using common product terms between multiple outputs might decrease QC significantly. In this paper, a modular and low QC design for a synchronous reversible [Formula: see text]-bit up/down counter with parallel load capability is presented. In this design, the common terms among multiple outputs are used efficiently, which leads to a low QC for the counter. A general formula to evaluate the QC of our proposed reversible counter is presented. This result shows that in our proposed design by increasing the number of bits of counter ([Formula: see text], the QC increases linearly, while in previous works by increasing the number of bits of counter, the QC increases exponentially.

scholarly journals Synchronous primary malignancies of the male urogenital tract

2014 ◽  
Vol 8 (5-6) ◽  
pp. 353 ◽  
Author(s):  
Abdelmounaim Qarro ◽  
Abdelghani Ammani ◽  
Khalil Bazine ◽  
Mohammed Najoui ◽  
Jamaleddine Samir ◽  
...  
Keyword(s):  
Prostate Cancer ◽  
Bladder Cancer ◽  
General Population ◽  
Bladder Tumour ◽  
Specific Antigen ◽  
Antigen Test ◽  
Prostate Specific Antigen Test ◽  
Increased Risk ◽  
Risk Of Progression ◽  
The Common

The finding of prostate cancer after a cystoprostatectomy for a bladder tumour can occur in up to 70% of cases. The incidence of prostate cancer in patients with a bladder tumour is 18 times higher than in the general population; moreover, the incidence of bladder cancer in patients with prostate cancer is 19 times higher than in the general population. This association can be explained by the common embryological origin of these organs, with molecular similarities. Other similarities between these two cancers are noted. They are multifocal and may be secondary to urinary stasis. However, this association does not seem responsible for an increased risk of progression of both diseases. The prognosis is related to the extension of each cancer. The stage and grade of bladder cancer are, in terms of prognosis, greater than those of prostate cancer. Most often, this is insignificant prostate cancer. Despite this, the prostate-specific antigen test should be administered to monitor patients after cystoprostatectomy.

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

2020 ◽  
pp. 2120003
Author(s):  
Zhengfeng Huang ◽  
Zian Su ◽  
Tianming Ni ◽  
Qi Xu ◽  
Haochen Qi ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Fault Tolerant ◽  
Cross Layer ◽  
Charge Sharing ◽  
Single Node ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Modular Redundancy ◽  
Voltage Swing

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

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