Room-temperature carrier transport in high-performance short-channel Silicon nanowire MOSFETs

2012 ◽  
Author(s):  
Amlan Majumdar ◽  
Sarunya Bangsaruntip ◽  
Guy M. Cohen ◽  
Lynne M. Gignac ◽  
Michael Guillorn ◽  
...  
Keyword(s):  
High Performance ◽  
Carrier Transport ◽  
Room Temperature ◽  
Silicon Nanowire ◽  
Short Channel ◽  
Nanowire Mosfets

Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs

2010 ◽  
Vol 31 (9) ◽  
pp. 903-905 ◽  
Author(s):  
Sarunya Bangsaruntip ◽  
Guy M. Cohen ◽  
Amlan Majumdar ◽  
Jeffrey W. Sleight
Keyword(s):  
Silicon Nanowire ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Nanowire Mosfets

Fabrication and Electronic Characteristics of Silicon Nanowire MOSFETs

2008 ◽  
Vol 1080 ◽  
Author(s):  
Hironori Yoshioka ◽  
Yuichiro Nanen ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Room Temperature ◽  
Silicon Nanowire ◽  
Subthreshold Slope ◽  
Low Field ◽  
Field Mobility ◽  
Gate Control ◽  
Bottom Width ◽  
Nanowire Mosfets ◽  
Soi Substrates ◽  
Low Field Mobility

ABSTRACTThe n-type silicon nanowire MOSFETs with a nanowire shape being triangular or trapezoidal, have been fabricated on SOI substrates and characterized. The height and bottom-width of the triangular nanowire has been 10 nm and 19 nm, respectively. The devices have shown good gate control, such as a nearly ideal subthreshold slope of 63 mV/decade, high Ion/Ioff ratio of 107, and small drain-induced barrier lowering of 5 mV/V at room temperature. The low field mobility of triangular nanowire has been estimated to be 130 cm2/V·s and shown no difference with the change of the nanowire shape and direction within the investigated range.

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

2013 ◽  
Vol 84 ◽  
pp. 46-52 ◽  
Author(s):  
M. Koyama ◽  
M. Cassé ◽  
R. Coquand ◽  
S. Barraud ◽  
C. Vizioz ◽  
...  
Keyword(s):  
Carrier Transport ◽  
Silicon Nanowire ◽  
Nanowire Mosfets

(Invited) High Performance and Highly Uniform Metal Hi-K Gate-All-Around Silicon Nanowire MOSFETs

2019 ◽  
Vol 28 (1) ◽  
pp. 179-189 ◽  
Author(s):  
Jeffrey W. Sleight ◽  
Sarunya Bangsaruntip ◽  
Guy Cohen ◽  
Amlan Majumdar ◽  
Ying Zhang ◽  
...  
Keyword(s):  
High Performance ◽  
Silicon Nanowire ◽  
Nanowire Mosfets ◽  
Highly Uniform

Co-planar two-dimensional Metal-Insulator-Semiconductor Capacitor: Numerical study of the device electrostatics.

2017 ◽  
Author(s):  
Varun Bheemireddy
Keyword(s):  
Space Charge ◽  
High Performance ◽  
Numerical Study ◽  
2D Materials ◽  
Space Charge Density ◽  
Two Dimensional ◽  
Short Channel ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
New Family

The two-dimensional(2D) materials are highly promising candidates to realise elegant and e cient transistor. In the present letter, we conjecture a novel co-planar metal-insulator-semiconductor(MIS) device(capacitor) completely based on lateral 2D materials architecture and perform numerical study of the capacitor with a particular emphasis on its di erences with the conventional 3D MIS electrostatics. The space-charge density features a long charge-tail extending into the bulk of the semiconductor as opposed to the rapid decay in 3D capacitor. Equivalently, total space-charge and semiconductor capacitance densities are atleast an order of magnitude more in 2D semiconductor. In contrast to the bulk capacitor, expansion of maximum depletion width in 2D semiconductor is observed with increasing doping concentration due to lower electrostatic screening. The heuristic approach of performance analysis(2D vs 3D) for digital-logic transistor suggest higher ON-OFF current ratio in the long-channel limit even without third dimension and considerable room to maximise the performance of short-channel transistor. The present results could potentially trigger the exploration of new family of co-planar at transistors that could play a signi significant role in the future low-power and/or high performance electronics.<br>

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