Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving

2008 ◽  
Author(s):  
Rui Gong ◽  
Kui Dai ◽  
Zhiying Wang
Keyword(s):  
Chip Multiprocessor ◽  
Fault Recovery ◽  
Transient Fault ◽  
On Chip ◽  
Dual Core

Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery

2007 ◽  
Vol 18 (8) ◽  
pp. 1080-1093 ◽  
Author(s):  
Yi Ma ◽  
Hongliang Gao ◽  
Martin Dimitrov ◽  
Huiyang Zhou
Keyword(s):  
Power Efficiency ◽  
Fault Recovery ◽  
Transient Fault ◽  
Dual Core

Investigation of transient fault effects in synchronous and asynchronous Network on Chip router

2011 ◽  
Vol 57 (1) ◽  
pp. 61-68 ◽  
Author(s):  
Pooria M. Yaghini ◽  
Ashkan Eghbal ◽  
Hossein Pedram ◽  
Hamid Reza Zarandi
Keyword(s):  
Network On Chip ◽  
Transient Fault ◽  
Asynchronous Network ◽  
On Chip

Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors

2014 ◽  
Author(s):  
Jian Fu ◽  
Qiang Yang ◽  
Raphael Poss ◽  
Chris R. Jesshope ◽  
Chunyuan Zhang
Keyword(s):  
Low Cost ◽  
Fault Recovery ◽  
Multithreaded Processors ◽  
Transient Fault ◽  
Recovery Scheme

Hardware/software support for adaptive work-stealing in on-chip multiprocessor

2010 ◽  
Vol 56 (8) ◽  
pp. 392-406 ◽  
Author(s):  
Quentin Meunier ◽  
Frédéric Pétrot ◽  
Jean-Louis Roch
Keyword(s):  
Chip Multiprocessor ◽  
Work Stealing ◽  
Software Support ◽  
On Chip ◽  
Adaptive Work

Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

2014 ◽  
Vol 29 (1) ◽  
pp. 21-37 ◽  
Author(s):  
Fang Lv ◽  
Hui-Min Cui ◽  
Lei Wang ◽  
Lei Liu ◽  
Cheng-Gang Wu ◽  
...  
Keyword(s):  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
Batch Mode ◽  
On Chip

scholarly journals Energy characteristic of a processor allocator and a network-on-chip

2011 ◽  
Vol 21 (2) ◽  
pp. 385-399 ◽  
Author(s):  
Dawid Zydek ◽  
Henry Selvaraj ◽  
Grzegorz Borowik ◽  
Tadeusz Łuba
Keyword(s):  
Energy Characteristic ◽  
Network On Chip ◽  
Energy Model ◽  
Chip Multiprocessor ◽  
Energy Estimation ◽  
Processing Elements ◽  
Chip Processing ◽  
On Chip ◽  
Allocation Algorithms ◽  
2D Torus

Energy characteristic of a processor allocator and a network-on-chip Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

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