Investigation of transient fault effects in synchronous and asynchronous Network on Chip router

Pooria M. Yaghini; Ashkan Eghbal; Hossein Pedram; Hamid Reza Zarandi

doi:10.1016/j.sysarc.2010.10.003

Investigation of transient fault effects in synchronous and asynchronous Network on Chip router

Journal of Systems Architecture ◽

10.1016/j.sysarc.2010.10.003 ◽

2011 ◽

Vol 57 (1) ◽

pp. 61-68 ◽

Cited By ~ 8

Author(s):

Pooria M. Yaghini ◽

Ashkan Eghbal ◽

Hossein Pedram ◽

Hamid Reza Zarandi

Keyword(s):

Network On Chip ◽

Transient Fault ◽

Asynchronous Network ◽

On Chip

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Power analysis for asynchronous network-on-chip

IEEJ Transactions on Electrical and Electronic Engineering ◽

10.1002/tee.21921 ◽

2013 ◽

Vol 8 (S1) ◽

pp. S72-S80

Author(s):

Mohamed A. Abd El Ghany ◽

Gursharan Reehal ◽

Mohammed Ismail

Keyword(s):

Power Analysis ◽

Network On Chip ◽

Asynchronous Network ◽

On Chip

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Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.11 ◽

2013 ◽

Cited By ~ 1

Author(s):

Takahiro Hanyu ◽

Yuma Watanabe ◽

Atsushi Matsumoto

Keyword(s):

High Speed ◽

Network On Chip ◽

Asynchronous Network ◽

Wire Delay ◽

On Chip ◽

Delay Information

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Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation

Microprocessors and Microsystems ◽

10.1016/j.micpro.2018.05.003 ◽

2018 ◽

Vol 60 ◽

pp. 173-184

Author(s):

Charles Effiong ◽

Gilles Sassatelli ◽

Abdoulaye Gamatie

Keyword(s):

Resource Allocation ◽

Network On Chip ◽

Dynamic Resource Allocation ◽

Power Efficient ◽

Asynchronous Network ◽

Dynamic Resource ◽

On Chip

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Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems

IEEE Consumer Electronics Magazine ◽

10.1109/mce.2019.2892243 ◽

2019 ◽

Vol 8 (3) ◽

pp. 50-54 ◽

Cited By ~ 1

Author(s):

Ayas Kanta Swain ◽

Anil Kumar Rajput ◽

Kamala Kanta Mahapatra

Keyword(s):

Network On Chip ◽

Consumer Electronics ◽

Asynchronous Network ◽

And Performance ◽

On Chip

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High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip

Proceedings of 2010 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2010.5538027 ◽

2010 ◽

Cited By ~ 2

Author(s):

Naoya Onizawa ◽

Takahiro Hanyu

Keyword(s):

High Throughput ◽

Network On Chip ◽

Asynchronous Network ◽

On Chip

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Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2008.0072 ◽

2009 ◽

Vol 3 (5) ◽

pp. 487 ◽

Cited By ~ 15

Author(s):

X.-T. Tran ◽

Y. Thonnart ◽

J. Durupt ◽

V. Beroulle ◽

C. Robach

Keyword(s):

Test Pattern ◽

Network On Chip ◽

Pattern Generation ◽

Test Pattern Generation ◽

Design For Test ◽

Asynchronous Network ◽

On Chip

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H2A: A hardened asynchronous network on chip

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) ◽

10.1109/sbcci.2013.6644865 ◽

2013 ◽

Cited By ~ 1

Author(s):

Julian Pontes ◽

Ney Calazans ◽

Pascal Vivet

Keyword(s):

Network On Chip ◽

Asynchronous Network ◽

On Chip

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Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping

Vlsi-Soc: From Systems To Silicon - IFIP International Federation for Information Proc ◽

10.1007/978-0-387-73661-7_13 ◽

2007 ◽

pp. 195-207 ◽

Cited By ~ 2

Author(s):

Jérôme Quartana ◽

Laurent Fesquet ◽

Marc Renaudin

Keyword(s):

Rapid Prototyping ◽

Network On Chip ◽

Asynchronous Network ◽

On Chip ◽

Gals Systems

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Virtual synaptic interconnect using an asynchronous network-on-chip

2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence) ◽

10.1109/ijcnn.2008.4634181 ◽

2008 ◽

Cited By ~ 22

Author(s):

Alexander D. Rast ◽

Shufan Yang ◽

Mukaram Khan ◽

Steve B. Furber

Keyword(s):

Network On Chip ◽

Asynchronous Network ◽

On Chip

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Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip

IEICE Transactions on Information and Systems ◽

10.1587/transinf.2013lop0024 ◽

2014 ◽

Vol E97.D (9) ◽

pp. 2304-2311 ◽

Cited By ~ 2

Author(s):

Akira MOCHIZUKI ◽

Hirokatsu SHIRAHAMA ◽

Yuma WATANABE ◽

Takahiro HANYU

Keyword(s):

Energy Efficient ◽

Current Mode ◽

Network On Chip ◽

Communication Link ◽

Asynchronous Network ◽

On Chip

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