Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance

2020 ◽  
Author(s):  
Karthik Sangaiah
Keyword(s):  
Network On Chip ◽  
Chip Multiprocessor ◽  
On Chip

scholarly journals Energy characteristic of a processor allocator and a network-on-chip

2011 ◽  
Vol 21 (2) ◽  
pp. 385-399 ◽  
Author(s):  
Dawid Zydek ◽  
Henry Selvaraj ◽  
Grzegorz Borowik ◽  
Tadeusz Łuba
Keyword(s):  
Energy Characteristic ◽  
Network On Chip ◽  
Energy Model ◽  
Chip Multiprocessor ◽  
Energy Estimation ◽  
Processing Elements ◽  
Chip Processing ◽  
On Chip ◽  
Allocation Algorithms ◽  
2D Torus

Energy characteristic of a processor allocator and a network-on-chip Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

EFFICIENT SCHEME FOR CONGESTION CONTROL IN NETWORK-ON-CHIP WITH QoS CONSIDERATION

2014 ◽  
Vol 23 (09) ◽  
pp. 1450120 ◽  
Author(s):  
ADEL SOUDANI ◽  
AHMED ALDAMMAS ◽  
ABDULLAH AL-DHELAAN
Keyword(s):  
Network On Chip ◽  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
Signaling Mechanism ◽  
Qos Management ◽  
Efficient Scheme ◽  
High Bandwidth ◽  
On Chip ◽  
Internal Architecture

Embedded distributed multimedia applications based on the use of on-chip networks for communication and messages exchange requires specific and enhanced quality of service (QoS) management. To reach the desired performances at the application level, the network-on-chip (NoC) router should implement per flit handling strategy with wide granularity. This purpose requires an enhanced internal architecture that ensures from one hand a specific management according to a service classification and from the other hand, it enhances the routing process. In this context, this paper proposes a new mechanism for QoS management in NoC. This mechanism is based on the use of central memory where flits are in-queued according to their class of service. This scheme enables an optimal flit scheduling phase and provides more capabilities to drop low important flits when the router shows congestion state symptoms. The paper presents, also, a protocol structure that fills with this architecture and introduces a signaling mechanism to make efficient the QoS management through the proposed architecture. The circuit performances and its adaptability to achieve QoS with low power processing and high bandwidth in on chip multiprocessor systems will be studied in this paper.

Network-on-Chip virtualization in Chip-Multiprocessor Systems

2012 ◽  
Vol 58 (3-4) ◽  
pp. 126-139 ◽  
Author(s):  
Francisco Triviño ◽  
José L. Sánchez ◽  
Francisco J. Alfaro ◽  
José Flich
Keyword(s):  
Network On Chip ◽  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
On Chip

A New Optical Network-on-Chip Architecture for Chip Multiprocessor

2015 ◽  
Author(s):  
Xiuhua Li ◽  
Kang Wang ◽  
Ke Chen ◽  
Huaxi Gu ◽  
Liang song ◽  
...  
Keyword(s):  
Optical Network ◽  
Network On Chip ◽  
Chip Multiprocessor ◽  
On Chip

scholarly journals Improved Ant Colony Algorithm Based on Task Scale in Network on Chip (NoC) Mapping

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 6 ◽  
Author(s):  
Juan Fang ◽  
Tingwen Yu ◽  
Zelin Wei
Keyword(s):  
Ant Colony Algorithm ◽  
Mapping Method ◽  
Network On Chip ◽  
Ant Colony ◽  
Mapping Algorithm ◽  
Network Latency ◽  
Bus Structure ◽  
Communication Distance ◽  
On Chip

Multi-core processors integrate with multiple computing units on one chip. This technology is increasingly mature, and communication between cores has become the largest research hotspot. As the number of cores continues to increase, the humble bus structure can no longer play the role of multi-core processors. Network on chip (NoC) connects components through routing, which greatly enhances the efficiency of communication. However, the communication power it consumes and network latency are issues that cannot be ignored. An efficient mapping algorithm is an effective method to reduce the communication power and network latency. This paper proposes a mapping method. First, the task is divided depending on the scale of the task. When the task scale is small, to reduce the communication distance between resource nodes, a given NoC substructure is selected to map the task; when the task scale is large, to reduce the communication between tasks, the tasks are clustered and tasks with dependencies are divided into the same resource node. Then combine with an improving ant colony algorithm (ACO) for mapping. The method proposed is being experimentally verified on NoC platforms of different scales. The experimental results show that the method proposed is very effectual for reducing communication power and network latency during NoC mapping.

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