Reconfigurable Circuit design using evolvable hardware chip for illumination tolerant image enhancement

2008 ◽  
Author(s):  
A. Guruva Reddy ◽  
M.N. Giri Prasad ◽  
K. Sri Rama Krishna
Keyword(s):  
Image Enhancement ◽  
Circuit Design ◽  
Evolvable Hardware ◽  
Reconfigurable Circuit

The Study on Evolvable Electrical Circuit Design Based on FPGA

2012 ◽  
Vol 433-440 ◽  
pp. 5494-5499
Author(s):  
Wen Wei Yu ◽  
Zhi Wen Chen
Keyword(s):  
Evolutionary Algorithm ◽  
Circuit Design ◽  
Processing Speed ◽  
Block Diagram ◽  
Electrical Circuit ◽  
Experimental Results ◽  
Evolvable Hardware ◽  
Probability Vector ◽  
String Processing ◽  
Diagram Design

The traditional evolutionary algorithm needs a lot of storage and handling ability in embedded logic project. Candidate’s solutions through the population, rather than the probability of vector of save memory and bite string processing. Concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm is proposed. This paper proposes a method of realizing the standard FPGA concise evolutionary algorithm with a few changes to improve search powers. A data flow and a block diagram design, this paper describes the show. Experimental results show that the requirements (logical block) need to implement, building processing speed and solution for the power evolvable hardware CEA.

Intrinsic Evolvable Hardware Structures

2010 ◽  
pp. 160-186
Author(s):  
Laurentiu Ionescu ◽  
Alin Mazare ◽  
Gabriel Iana ◽  
Gheorghe Serban ◽  
Ionel Bostan
Keyword(s):  
Genetic Algorithm ◽  
Evolvable Hardware ◽  
Concept Design ◽  
Main Section ◽  
Reconfigurable Circuits ◽  
Reconfigurable Circuit ◽  
Research Areas ◽  
Application Requirements ◽  
Hardware Reconfiguration ◽  
Hardware Structure

The main target of this chapter is to present the intrinsic evolvable hardware structures: concept, design and applications. The intrinsic evolvable hardware structures concept join more research areas like: bio–inspired searching methods (evolutionary algorithms), optimization of algorithms by parallel processing and reconfigurable circuits. First, a general overview about intrinsic evolvable hardware structure is presented. The intrinsic evolvable hardware structure consists of two main modules: hardware genetic algorithm and dynamic reconfigurable circuit. The hardware genetic algorithm searches the configuration that makes the reconfigurable circuit to correctly respond to application requirements. The background section present the genetic algorithm concept as a bio-inspired search solution, the hardware reconfiguration concept with sub areas classifications and the research directions in the evolvable hardware structures areas with application examples. The main section presents the design solutions for hardware implementation of genetic algorithm and for the reconfigurable circuit. Finally, several applications are presented that illustrate the usefulness of the intrinsic evolvable hardware structure.

scholarly journals VHDL IMPLEMENTATION OF GENETIC ALGORITHM FOR 2-BIT ADDER

2014 ◽  
pp. 12-17
Author(s):  
VEDAVATHI. A ◽  
MEENA. K.V ◽  
GAYATRI MALHOTRA
Keyword(s):  
Genetic Algorithm ◽  
Circuit Design ◽  
Evolvable Hardware ◽  
Evolutionary Design ◽  
Space Vehicles ◽  
Cartesian Genetic Programming ◽  
System Architectures ◽  
Deep Space Exploration ◽  
Unpredictable Environment ◽  
Circuit Configuration

Future planetary and deep space exploration demands that the space vehicles should have robust system architectures and be reconfigurable in unpredictable environment. The Evolutionary design of electronic circuits, or Evolvable hardware (EHW), is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under control of Evolutionary algorithms. The most commonly used evolutionary algorithm is Genetic Algorithm. The paper discusses on Cartesian Genetic Programming for evolving gate level designs and proposes Evolvable unit for 2-bit adder based on Genetic Algorithm.

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