VHDL IMPLEMENTATION OF GENETIC ALGORITHM FOR 2-BIT ADDER

International Journal of Electronics and Electical Engineering ◽

10.47893/ijeee.2014.1120 ◽

2014 ◽

pp. 12-17

Author(s):

VEDAVATHI. A ◽

MEENA. K.V ◽

GAYATRI MALHOTRA

Keyword(s):

Genetic Algorithm ◽

Circuit Design ◽

Evolvable Hardware ◽

Evolutionary Design ◽

Space Vehicles ◽

Cartesian Genetic Programming ◽

System Architectures ◽

Deep Space Exploration ◽

Unpredictable Environment ◽

Circuit Configuration

Future planetary and deep space exploration demands that the space vehicles should have robust system architectures and be reconfigurable in unpredictable environment. The Evolutionary design of electronic circuits, or Evolvable hardware (EHW), is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under control of Evolutionary algorithms. The most commonly used evolutionary algorithm is Genetic Algorithm. The paper discusses on Cartesian Genetic Programming for evolving gate level designs and proposes Evolvable unit for 2-bit adder based on Genetic Algorithm.

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GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning

Electronics ◽

10.3390/electronics10091032 ◽

2021 ◽

Vol 10 (9) ◽

pp. 1032

Author(s):

Hyoungsik Nam ◽

Young In Kim ◽

Jina Bae ◽

Junhee Lee

Keyword(s):

Reinforcement Learning ◽

Circuit Design ◽

Logic Gates ◽

Connection Matrix ◽

Design Framework ◽

Network Layers ◽

Learning Speed ◽

Fully Connected ◽

Automated Circuit Design ◽

Circuit Configuration

This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection of circuit elements, the action masking scheme is employed. It also reduces the size of the action space leading to the improvement on the learning speed. The GateRL consists of an agent for the action and an environment for state, mask, and reward. State and reward are generated from a connection matrix that describes the current circuit configuration, and the mask is obtained from a masking matrix based on constraints and current connection matrix. The action is given rise to by the deep Q-network of 4 fully connected network layers in the agent. In particular, separate replay buffers are devised for success transitions and failure transitions to expedite the training process. The proposed network is trained with 2 inputs, 1 output, 2 NMOS transistors, and 2 PMOS transistors to design all the target logic gates, such as buffer, inverter, AND, OR, NAND, and NOR. Consequently, the GateRL outputs one-transistor buffer, two-transistor inverter, two-transistor AND, two-transistor OR, three-transistor NAND, and three-transistor NOR. The operations of these resultant logics are verified by the SPICE simulation.

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