Novel Device Structures for Charge Trap Flash Memories

2006 ◽  
Author(s):  
Byung-gook Park ◽  
Il Park ◽  
Jung-hoon Lee ◽  
Byung Choi
Keyword(s):  
Flash Memories ◽  
Charge Trap ◽  
Novel Device ◽  
Device Structures

Electrical degradation mechanisms of nanoscale charge trap flash memories due to trapped charge in the oxide layer

2015 ◽  
Vol 67 (3) ◽  
pp. 533-536
Author(s):  
Kyoung Wook Koh ◽  
Dong Hun Kim ◽  
Ju Tae Ryu ◽  
Tae Whan Kim ◽  
Keon-Ho Yoo
Keyword(s):  
Oxide Layer ◽  
Degradation Mechanisms ◽  
Flash Memories ◽  
Charge Trap ◽  
Electrical Degradation ◽  
Trapped Charge

Zone Melting Recrystallization of InSb Films on Oxidized Si Wafers

1983 ◽  
Vol 23 ◽  
Author(s):  
C.C. Wong ◽  
C.J. Keavney ◽  
H.A. Atwater ◽  
C.V. Thompson ◽  
H.I. Smith
Keyword(s):  
Thin Films ◽  
Single Crystal ◽  
Eutectic Structure ◽  
Zone Melting ◽  
Molten Zone ◽  
Si Substrates ◽  
Novel Device ◽  
Device Structures ◽  
Insb Thin Films ◽  
Selection Of

ABSTRACTInSb thin films on oxidized Si wafers have been recrystallized using a strip heater to generate and scan a narrow molten zone across the film. Grains up to 3 × 10 mm have been produced. Crystallization proceeds in a faceted cellular fashion, the excess solute (Sb) being rejected into subboundaries which often lie along low-index crystallographic directions. A InSb-Sb eutectic structure forms at the subboundaries. The width of the single-crystal InSb between subboundaries is approximately 75 μm. The techniques of planar constriction and subboundary entrainment have been extended to InSb for the selection of single grains and the orelocation of subboundaries. This technology of producing InSb thin films on oxidized Si substrates max, be extendable to other III-V materials, and could lead to novel device structures through the integration of Si and III-V compound devices on the same substrate.

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

2010 ◽  
Vol 49 (8) ◽  
pp. 084301 ◽  
Author(s):  
Doo-Hyun Kim ◽  
Seongjae Cho ◽  
Dong Hua Li ◽  
Jang-Gn Yun ◽  
Jung Hoon Lee ◽  
...  
Keyword(s):  
Flash Memories ◽  
Charge Trap

Improved electrical properties of charge trap flash memories having a patterned surface in a Si3N4 trap layer

2011 ◽  
Author(s):  
H. M. An ◽  
J. W. Yang ◽  
H. D. Kim ◽  
J. W. Son ◽  
W. J. Cho ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Flash Memories ◽  
Charge Trap ◽  
Patterned Surface
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