The impact of forming temperature on material and electrical characteristics of nickel silicide gate electrode

2006 ◽  
Author(s):  
Xiaonan Shan ◽  
Yimao Cai ◽  
Chuan Xu ◽  
Yan Li ◽  
Ru Huang
Keyword(s):  
Nickel Silicide ◽  
Electrical Characteristics ◽  
Gate Electrode ◽  
Forming Temperature ◽  
The Impact

SILICON ON RAISED INSULATOR FIELD EFFECT DIODE (SORI-FED) FOR ALLEVIATING SCALING PROBLEM IN FED

2014 ◽  
Vol 28 (05) ◽  
pp. 1450038 ◽  
Author(s):  
MAHDI VADIZADEH ◽  
MORTEZA FATHIPOUR ◽  
GHAFAR DARVISH
Keyword(s):  
Delay Time ◽  
Field Effect ◽  
Channel Length ◽  
Gate Delay ◽  
Electrical Characteristics ◽  
Band To Band Tunneling ◽  
Main Components ◽  
Channel Lengths ◽  
Length Scaling ◽  
The Impact

One of the main shortcomings in a field effect diode (FED) is its scaling. Use of an oxide layer in the channel is proposed to enhance the control of the gate on the channel carriers. This is the so-called silicon on raised insulator FED (SORI-FFD) structure. The Shockley–Read–Hall (SRH) mechanism is one of the main components of leakage current in FED devices. The potential induced by the gates in the OFF-state of a SORI-FFD, is larger than that induced by the gates of a regular FED. This reduces, SRH recombination rate. Hence, OFF-state characteristics of the SORI-FED device improves. We evaluate the impact of band-to-band tunneling (BTBT) on the electrical characteristics of Modified FED (M-FED).We show that for channel lengths of 35 nm and lower this device does not turn off. While, the proposed structure makes device channel length scaling possible down to 15 nm. We will also compare electrical characteristics of SORI-FED and M-FED using three metrics: gate delay time versus channel length, gate delay time versus I ON /I OFF ratio and energy-delay product versus channel length. Benchmarking results show the proposed FED structure provides improvement in I ON /I OFF ratio and holds promise for future logic transistor applications.

Physical and electrical characteristics of HfN gate electrode for advanced MOS devices

2003 ◽  
Vol 24 (4) ◽  
pp. 230-232 ◽  
Author(s):  
H.Y. Yu ◽  
H.F. Lim ◽  
J.H. Chen ◽  
M.F. Li ◽  
Chunxiang Zhu ◽  
...  
Keyword(s):  
Electrical Characteristics ◽  
Gate Electrode ◽  
Mos Devices

scholarly journals The impact of channel fin width on electrical characteristics of Si-FinFET

2022 ◽  
Vol 12 (1) ◽  
pp. 201
Author(s):  
Yousif Atalla ◽  
Yasir Hashim ◽  
Abdul Nasir Abd. Ghafar
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Environmental Temperature ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Working Temperature ◽  
Effect Transistor ◽  
The Impact ◽  
The Ideal

<span>This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W<sub>F</sub>=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.</span>

Design and Characterization of a Novel Dual-Gate 3.3 Kv 4H-Sic JFET

2013 ◽  
Vol 740-742 ◽  
pp. 938-941
Author(s):  
Florian Chevalier ◽  
P. Brosselard ◽  
D. Tournier ◽  
G. Grosset ◽  
L. Dupuy ◽  
...  
Keyword(s):  
Design Methodology ◽  
Vertical Channel ◽  
Optimal Structure ◽  
Electrical Characteristics ◽  
Gate Electrode ◽  
Thermal Oxide ◽  
Dual Gate

This paper presents the methodology for the design of a novel 4H-SiC JFET structure able to sustain 3.3 kV. Comparisons between simulation and characterization res will be made. Taken into account the process limitation, we will also discuss the critical steps and their impact on the electrical characteristics. A design methodology based on Baliga's criterion is proposed to obtain the optimal structure. A 50 nm thick thermal oxide grown above vertical channel and the use of a buried p+ layer as second gate electrode are brand new in front of what is found in literature.

Metastable Defect Distributions in CIGS Solar Cells and Their Impact on Device Efficiency

2007 ◽  
Vol 1012 ◽  
Author(s):  
Malgorzata Igalson
Keyword(s):  
Carrier Transport ◽  
Theoretical Calculations ◽  
Electrical Characteristics ◽  
Current Voltage ◽  
Device Efficiency ◽  
Current Voltage Characteristics ◽  
Cigs Solar Cells ◽  
Metastable Effects ◽  
The Impact ◽  
Metastable Defect

AbstractMetastabilities in the electrical characteristics of CIGS devices are commonly observed phenomena originating from persistent changes of shallow and deep levels distributions within the absorber. We examine characteristic changes induced by voltage bias and light together with their relaxation behavior and interpret them as the consequences of a negative-U type of centers predicted by theoretical calculations of Lany and Zunger. It is shown how the properties of these centers justify a model of p+ layer explaining specific features of light and dark current-voltage characteristics. The discussion showing the impact of various charge distributions on carrier transport is presented. The arguments are provided, that centers responsible for metastable effects are also to blame for majority of photovoltaic losses exhibited in various devices.

Fabrication and electrical characteristics of carbon nanotube field emission microcathodes with an integrated gate electrode

2001 ◽  
Vol 13 (1) ◽  
pp. 1-4 ◽  
Author(s):  
G Pirio ◽  
P Legagneux ◽  
D Pribat ◽  
K B K Teo ◽  
M Chhowalla ◽  
...  
Keyword(s):  
Carbon Nanotube ◽  
Field Emission ◽  
Electrical Characteristics ◽  
Gate Electrode

Phase Inhomogeneity and Electrical Characteristics of Nickel Silicide Schottky Contacts Formed on 4H-SiC

2009 ◽  
Vol 615-617 ◽  
pp. 577-580 ◽  
Author(s):  
Irina P. Nikitina ◽  
Konstantin Vassilevski ◽  
Alton B. Horsfall ◽  
Nicolas G. Wright ◽  
Anthony G. O'Neill ◽  
...  
Keyword(s):  
Nickel Silicide ◽  
Schottky Contacts ◽  
Electrical Characteristics ◽  
Adhesion Layer ◽  
Temperature Range ◽  
Barrier Heights ◽  
Phase Inhomogeneity ◽  
Layer 4 ◽  
State Chemical ◽  
Nisi Phase

Nickel silicide Schottky contacts were formed on 4H-SiC by consecutive deposition of a titanium adhesion layer, 4 nm thick, and nickel, 100 nm thick, followed by annealing at temperatures from 600 to 750 °C. It was found that contacts with barrier heights of 1.45 eV, consisting mainly of NiSi phase, formed in the 600-660 °C temperature range, while annealing at around 750 °C led to the formation of Ni2Si phase with barrier heights of 1.1 eV. Annealing at intermediate temperatures resulted in the nucleation of Ni2Si grains embedded in the NiSi film which were directly observed by micro-Raman mapping. It was concluded that the thermodynamically unfavourable NiSi phase appeared in the 600-660 °C temperature range due to the fact that the solid state chemical reaction between Ni and SiC at these temperatures is controlled by nickel diffusion through the titanium barrier.

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