Board Level Drop Test Reliability for MCP Package

2006 ◽  
Author(s):  
Jing Zhang ◽  
Maohua Du ◽  
Nufeng Feng ◽  
Taekoo Lee
Keyword(s):  
Drop Test ◽  
Test Reliability ◽  
Board Level

Board level drop test reliability of IC packages

2005 ◽  
Author(s):  
T.C. Chai ◽  
S. Quek ◽  
W.Y. Hnin ◽  
E.H. Wong ◽  
J. Chia ◽  
...  
Keyword(s):  
Drop Test ◽  
Test Reliability ◽  
Board Level

Effect of Solder Composition and Substrate Surface Finish on Board Level Drop Test Reliability

2005 ◽  
Author(s):  
Don-Son Jiang ◽  
Joe Hung ◽  
Yu-Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Solder Joint ◽  
Substrate Surface ◽  
Drop Impact ◽  
Drop Test ◽  
Test Reliability ◽  
Lead Free ◽  
Lead Free Solder ◽  
Snagcu Solder ◽  
Free Solder ◽  
Board Level

For handheld or portable telecommunication devices such as mobile phone, PDA, etc., board level joint reliability during drop impact is a great concern to simulate mishandling during usage. In general, solder composition and substrate surface finish would principally determine the solder joint reliability. Board level drop test reliability of two solder compositions (SnPb and lead free SnAgCu) and surface finishes (Ni/Au and OSP) were examined in this study. The result indicated SnAgCu lead free solder showed poorer reliability life than Sn-Pb solder during drop impact. The crack path in SnPb solder joint almost went through bulk solder near substrate side. However, another IMC/Ni interfacial failure mode near substrate side was found in SnAgCu solder to cause lower reliability. This difference could attribute to higher strength of SnAgCu solder and deformation with higher strain rate in drop test. Comparison between two surface finishes indicated Ni/Au is better than OSP in both SnPb and SnAgCu lead free solder joints. In SnAgCu lead free solder joint with OSP, there are thicker Cu6Sn5 IMC and many large Ag3Sn IMC plates in interface to degrade the interfacial bonding, so drop impact would easily cause the all cracks through IMC/Cu interface and then reduce the reliability.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test

2014 ◽  
Vol 936 ◽  
pp. 628-632 ◽  
Author(s):  
Guo Zheng Yuan ◽  
Xia Chen ◽  
Xue Feng Shu
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Ball Grid Array ◽  
Test Method ◽  
Drop Test ◽  
Test Reliability ◽  
Internal Crack ◽  
The Real ◽  
Plastic Ball ◽  
Free Drop

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

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